Choco OS  V.0.16.9.0
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oc_eth_lld.c
1 
29 #include <oc_eth_lld.h>
30 #include <oc_mem_lld.h>
31 #include <oc_bits.h>
32 #include <oc_module.h>
33 #include <oc_lsf.h>
34 #include <oc_stdtypes.h>
35 #include <oc_channels.h>
36 #include <oc_ba.h>
37 #include <oc_gpio_lld.h>
38 #include <oc_gpio_mslld.h>
39 #include <oc_clock_lld.h>
40 #include <string.h>
41 #include <oc_registers.h>
42 
48 #define _________________________________________MACROS_SECTION_____________________________________________________________________________
49 
50 #define DESCRIPTOR_LIST_SIZE 5
51 #define TIMEOUT ms(200)
52 #define MAX_PHY_ADDRESS 0x1F
53 #define MAX_PHY_REGISTER_ADDRESS 0x1F
54 #define MAX_PHY_REGISTER_DATA_VALUE 0xFFFF
55 #define ETH_Channel oC_Channel_ETH
56 #define IsRam(Address) (oC_LSF_IsRamAddress(Address) || oC_LSF_IsExternalAddress(Address))
57 #define IsRom(Address) oC_LSF_IsRomAddress(Address)
58 #define IsDma(Address) oC_LSF_IsDmaAddress(Address)
59 #define ETH_MACCR oC_Register(ETHERNET_MAC,ETH_MACCR)
60 #define ETH_MACFFR oC_Register(ETHERNET_MAC,ETH_MACFFR)
61 #define ETH_MACHTHR oC_Register(ETHERNET_MAC,ETH_MACHTHR)
62 #define ETH_MACHTLR oC_Register(ETHERNET_MAC,ETH_MACHTLR)
63 #define ETH_MACMIIAR oC_Register(ETHERNET_MAC,ETH_MACMIIAR)
64 #define ETH_MACMIIDR oC_Register(ETHERNET_MAC,ETH_MACMIIDR)
65 #define ETH_MACFCR oC_Register(ETHERNET_MAC,ETH_MACFCR)
66 #define ETH_MACVLANTR oC_Register(ETHERNET_MAC,ETH_MACVLANTR)
67 #define ETH_MACRWUFFR oC_Register(ETHERNET_MAC,ETH_MACRWUFFR)
68 #define ETH_MACPMTCSR oC_Register(ETHERNET_MAC,ETH_MACPMTCSR)
69 #define ETH_MACDBGR oC_Register(ETHERNET_MAC,ETH_MACDBGR)
70 #define ETH_MACSR oC_Register(ETHERNET_MAC,ETH_MACSR)
71 #define ETH_MACIMR oC_Register(ETHERNET_MAC,ETH_MACIMR)
72 #define ETH_MACA0HR oC_Register(ETHERNET_MAC,ETH_MACA0HR)
73 #define ETH_MACA0LR oC_Register(ETHERNET_MAC,ETH_MACA0LR)
74 #define ETH_MACA1HR oC_Register(ETHERNET_MAC,ETH_MACA1HR)
75 #define ETH_MACA1LR oC_Register(ETHERNET_MAC,ETH_MACA1LR)
76 #define ETH_MACA2HR oC_Register(ETHERNET_MAC,ETH_MACA2HR)
77 #define ETH_MACA2LR oC_Register(ETHERNET_MAC,ETH_MACA2LR)
78 #define ETH_MACA3HR oC_Register(ETHERNET_MAC,ETH_MACA3HR)
79 #define ETH_MACA3LR oC_Register(ETHERNET_MAC,ETH_MACA3LR)
80 #define ETH_MMCCR oC_Register(ETHERNET_MAC,ETH_MMCCR)
81 #define ETH_MMCRIR oC_Register(ETHERNET_MAC,ETH_MMCRIR)
82 #define ETH_MMCTIR oC_Register(ETHERNET_MAC,ETH_MMCTIR)
83 #define ETH_MMCRIMR oC_Register(ETHERNET_MAC,ETH_MMCRIMR )
84 #define ETH_MMCTIMR oC_Register(ETHERNET_MAC,ETH_MMCTIMR )
85 #define ETH_MMCTGFSCCR oC_Register(ETHERNET_MAC,ETH_MMCTGFSCCR )
86 #define ETH_MMCTGFMSCCR oC_Register(ETHERNET_MAC,ETH_MMCTGFMSCCR)
87 #define ETH_MMCTGFCR oC_Register(ETHERNET_MAC,ETH_MMCTGFCR )
88 #define ETH_MMCRFCECR oC_Register(ETHERNET_MAC,ETH_MMCRFCECR )
89 #define ETH_MMCRFAECR oC_Register(ETHERNET_MAC,ETH_MMCRFAECR )
90 #define ETH_MMCRGUFCR oC_Register(ETHERNET_MAC,ETH_MMCRGUFCR )
91 #define ETH_PTPTSCR oC_Register(ETHERNET_MAC,ETH_PTPTSCR )
92 #define ETH_PTPSSIR oC_Register(ETHERNET_MAC,ETH_PTPSSIR )
93 #define ETH_PTPTSHR oC_Register(ETHERNET_MAC,ETH_PTPTSHR )
94 #define ETH_PTPTSLR oC_Register(ETHERNET_MAC,ETH_PTPTSLR )
95 #define ETH_PTPTSHUR oC_Register(ETHERNET_MAC,ETH_PTPTSHUR )
96 #define ETH_PTPTSLIR oC_Register(ETHERNET_MAC,ETH_PTPTSLIR )
97 #define ETH_PTPTSAR oC_Register(ETHERNET_MAC,ETH_PTPTSAR )
98 #define ETH_PTPTTHR oC_Register(ETHERNET_MAC,ETH_PTPTTHR )
99 #define ETH_PTPTTLR oC_Register(ETHERNET_MAC,ETH_PTPTTLR )
100 #define ETH_PTPTSSR oC_Register(ETHERNET_MAC,ETH_PTPTSSR )
101 #define ETH_DMABMR oC_Register(ETHERNET_MAC,ETH_DMABMR )
102 #define ETH_DMATPDR oC_Register(ETHERNET_MAC,ETH_DMATPDR )
103 #define ETH_DMARPDR oC_Register(ETHERNET_MAC,ETH_DMARPDR )
104 #define ETH_DMARDLAR oC_Register(ETHERNET_MAC,ETH_DMARDLAR )
105 #define ETH_DMATDLAR oC_Register(ETHERNET_MAC,ETH_DMATDLAR )
106 #define ETH_DMASR oC_Register(ETHERNET_MAC,ETH_DMASR )
107 #define ETH_DMAOMR oC_Register(ETHERNET_MAC,ETH_DMAOMR )
108 #define ETH_DMAIER oC_Register(ETHERNET_MAC,ETH_DMAIER )
109 #define ETH_DMAMFBOCR oC_Register(ETHERNET_MAC,ETH_DMAMFBOCR )
110 #define ETH_DMARSWTR oC_Register(ETHERNET_MAC,ETH_DMARSWTR )
111 #define ETH_DMACHTDR oC_Register(ETHERNET_MAC,ETH_DMACHTDR )
112 #define ETH_DMACHRDR oC_Register(ETHERNET_MAC,ETH_DMACHRDR )
113 #define ETH_DMACHTBAR oC_Register(ETHERNET_MAC,ETH_DMACHTBAR )
114 #define ETH_DMACHRBAR oC_Register(ETHERNET_MAC,ETH_DMACHRBAR )
115 #define SYSCFG_PMC oC_Register(SYSCFG,SYSCFG_PMC)
116 #define RCC_AHB1ENR oC_Register(RCC,RCC_AHB1ENR)
117 
118 #undef _________________________________________MACROS_SECTION_____________________________________________________________________________
119 
125 #define _________________________________________TYPES_SECTION______________________________________________________________________________
126 
127 typedef struct
128 {
129  oC_Frequency_t Min;
130  oC_Frequency_t Max;
131 } ClockRange_t;
132 
133 typedef enum
134 {
135  ReceiveProcessState_Stopped = 0 ,
136  ReceiveProcessState_FetchingReceiveTransferDescriptor = 0x01 ,
137  ReceiveProcessState_WaitingForReceivePacket = 0x03 ,
138  ReceiveProcessState_SuspendedReceiveDescriptorUnavailable = 0x04 ,
139  ReceiveProcessState_ClosingReceiveDescriptor = 0x05 ,
140  ReceiveProcessState_TransferingReceivedPacketToHostMemory = 0x07 ,
141 } ReceiveProcessState_t;
142 
143 typedef enum
144 {
145  TransmitProcessState_Stopped = 0 ,
146  TransmitProcessState_FetchingTransmitTransferDescriptor = 0x01 ,
147  TransmitProcessState_WaitingForStatus = 0x02 ,
148  TransmitProcessState_ReadingDataFromHostToFifo = 0x03 ,
149  TransmitProcessState_SuspendedTransmitDescriptorUnavailable = 0x06 ,
150  TransmitProcessState_ClosingTransmitDescriptor = 0x07 ,
151 } TransmitProcessState_t;
152 
153 typedef struct
154 {
155  uint8_t TransmissionFinished:1;
156  uint8_t TransmissionStopped:1;
157  uint8_t TransmitBufferUnavailable:1;
158  uint8_t TransmitJabberTimeout:1;
159  uint8_t ReceiveOverflow:1;
160  uint8_t TransmitUnderflow:1;
161  uint8_t ReceiveFinished:1;
162  uint8_t ReceiveBufferUnavailable:1;
163  uint8_t ReceiveStopped:1;
164  uint8_t ReceiveWatchdogTimeout:1;
165  uint8_t DataTransferredToFifo:1;
166  uint8_t Reserved:2;
167  uint8_t FatalBusError:1;
168  uint8_t FirstDataReceived:1;
169  uint8_t AbnormalInterruptSummary:1;
170  uint8_t NormalInterruptSummary:1;
171  ReceiveProcessState_t ReceiveProcessState:3;
172  TransmitProcessState_t TransmitProcessState:3;
173  uint8_t ErrorDuringTransferDataByTx:1;
174  uint8_t ErrorDuringReadTransfer:1;
175  uint8_t ErrorDuringDescriptorAccess:1;
176  uint8_t Reserved2:1;
177  uint8_t MmcStatus:1;
178  uint8_t PmtStatus:1;
179  uint8_t TimeStampTriggerStatus:1;
180  uint8_t Reserved3:2;
181 } DmaStatus_t;
182 
183 struct Descriptor_t
184 {
185  union
186  {
187  struct
188  {
189  uint32_t DB:1;
190  uint32_t UF:1;
191  uint32_t ED:1;
192  uint32_t CC:4;
193  uint32_t VF:1;
194  uint32_t EC:1;
195  uint32_t LCO:1;
196  uint32_t NC:1;
197  uint32_t LCA:1;
198  uint32_t IPE:1;
199  uint32_t FF:1;
200  uint32_t JT:1;
201  uint32_t ES:1;
202  uint32_t IHE:1;
203  uint32_t TTSS:1;
204  uint32_t Reserved:2;
205  uint32_t TCH:1;
206  uint32_t TER:1;
207  uint32_t CIC:2;
208  uint32_t Reserved24:1;
209  uint32_t TTSSE:1;
210  uint32_t DP:1;
211  uint32_t DC:1;
212  uint32_t FS:1;
213  uint32_t LS:1;
214  uint32_t IC:1;
215  uint32_t OWN:1;
216  } Tx0;
217 
218  struct
219  {
220  uint32_t PCEESA:1;
221  uint32_t CE:1;
222  uint32_t DBE:1;
223  uint32_t RE:1;
224  uint32_t RWT:1;
225  uint32_t FT:1;
226  uint32_t LCO:1;
227  uint32_t IPHCETSV:1;
228  uint32_t LS:1;
229  uint32_t FS:1;
230  uint32_t VLAN:1;
231  uint32_t OE:1;
232  uint32_t LE:1;
233  uint32_t SAF:1;
234  uint32_t DE:1;
235  uint32_t ES:1;
236  uint32_t FL:14;
237  uint32_t AFM:1;
238  uint32_t OWN:1;
239  } Rx0;
240  uint32_t TDES0;
241  uint32_t RDES0;
242  };
243 
244  union
245  {
246  struct
247  {
248  uint32_t Buffer1ByteCount:13;
249  uint32_t Reserved1315:3;
250  uint32_t Buffer2ByteCount:13;
251  uint32_t Reserved3129:3;
252  } Tx1;
253  struct
254  {
255  uint32_t RBS:13;
256  uint32_t Reserved1313:1;
257  uint32_t RCH:1;
258  uint32_t RER:1;
259  uint32_t RBS2:13;
260  uint32_t Reserved2930:2;
261  uint32_t DIC:1;
262  } Rx1;
263  uint32_t TDES1;
264  uint32_t RDES1;
265  };
266 
267  union
268  {
269  oC_ETH_LLD_Frame_t* Frame;
270  uint32_t TimestampLow;
271  uint32_t TDES2;
272  };
273 
274  union
275  {
276  uint32_t TimestampHigh;
277  struct Descriptor_t* NextDescriptorAddress;
278  uint32_t Buffer2Address;
279  uint32_t TDES3;
280  };
281 
282  uint32_t TDES4;
283  uint32_t TDES5;
284  uint32_t TDES6;
285  uint32_t TDES7;
286 } ;
287 
288 #undef _________________________________________TYPES_SECTION______________________________________________________________________________
289 
290 
296 #define _________________________________________PROTOTYPES_SECTION_________________________________________________________________________
297 
298 static oC_ErrorCode_t ConnectPins ( const oC_ETH_LLD_Config_t * Config , oC_ETH_LLD_PHY_CommunicationInterface_t CommunicationInterface , oC_ETH_LLD_Result_t * outResult );
299 static oC_ErrorCode_t DisconnectPins ( oC_Pin_t * ConnectedPins , uint16_t ArraySize );
300 static oC_ErrorCode_t ConnectPin ( oC_Pin_t Pin , oC_PinFunction_t PinFunction , oC_Pin_t * outConnectedPinReference );
301 static oC_ErrorCode_t DisconnectPin ( oC_Pin_t Pin );
302 static oC_ErrorCode_t EnableClock ( oC_ETH_LLD_PHY_CommunicationInterface_t CommunicationInterface );
303 static oC_ErrorCode_t DisableClock ( void );
304 static oC_ErrorCode_t CheckPhyCommunicationInterface ( oC_ETH_LLD_PHY_CommunicationInterface_t CommunicationInterface );
305 
306 static oC_ErrorCode_t PerformMacRegisterAccessTest ( oC_Diag_t * Diag , void * Context );
307 
308 #undef _________________________________________PROTOTYPES_SECTION_________________________________________________________________________
309 
315 #define _________________________________________VARIABLES_SECTION__________________________________________________________________________
316 
317 static oC_ETH_LLD_PHY_CommunicationInterface_t ConfiguredPhyCommunicationInterface = oC_ETH_LLD_PHY_CommunicationInterface_None;
318 static uint32_t NumberOfConfiguredPhys = 0;
319 static oC_ETH_LLD_Descriptor_t TxDescriptor = NULL;
320 static oC_ETH_LLD_Descriptor_t RxDescriptor = NULL;
321 static oC_ETH_LLD_InterruptFunction_t InterruptHandler = NULL;
322 static DmaStatus_t* DmaStatus = (DmaStatus_t*)&ETH_DMASR->Value;
323 
324 static const oC_Diag_SupportedDiagData_t SupportedDiagsArray[] = {
325  { .Name = "MAC register access test" , .PerformFunction = PerformMacRegisterAccessTest } ,
326 };
327 
328 #undef _________________________________________VARIABLES_SECTION__________________________________________________________________________
329 
335 #define _________________________________________FUNCTIONS_SECTION__________________________________________________________________________
336 
337 //==========================================================================================================================================
342 //==========================================================================================================================================
343 oC_ErrorCode_t oC_ETH_LLD_TurnOnDriver( void )
344 {
345  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
346 
347  oC_MCS_EnterCriticalSection();
348 
349  if(oC_Module_TurnOffVerification(&errorCode , oC_Module_ETH_LLD))
350  {
351  oC_Module_TurnOn(oC_Module_ETH_LLD);
352 
353  ConfiguredPhyCommunicationInterface = oC_ETH_LLD_PHY_CommunicationInterface_None;
354  NumberOfConfiguredPhys = 0;
355  TxDescriptor = NULL;
356  RxDescriptor = NULL;
357  InterruptHandler = NULL;
358  errorCode = oC_ErrorCode_None;
359  }
360 
361  oC_MCS_ExitCriticalSection();
362 
363  return errorCode;
364 }
365 
366 //==========================================================================================================================================
371 //==========================================================================================================================================
372 oC_ErrorCode_t oC_ETH_LLD_TurnOffDriver( void )
373 {
374  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
375 
376  oC_MCS_EnterCriticalSection();
377 
378  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_ETH_LLD))
379  {
380  oC_Module_TurnOff(oC_Module_ETH_LLD);
381  errorCode = oC_ErrorCode_None;
382  }
383 
384  oC_MCS_ExitCriticalSection();
385 
386  return errorCode;
387 }
388 
389 //==========================================================================================================================================
394 //==========================================================================================================================================
395 oC_ErrorCode_t oC_ETH_LLD_SetInterruptHandler( oC_ETH_LLD_InterruptFunction_t Function )
396 {
397  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
398 
399  oC_MCS_EnterCriticalSection();
400 
401  if(oC_Module_TurnOnVerification(&errorCode, oC_Module_ETH_LLD))
402  {
403  if(
404  ErrorCondition( IsRam(Function) || IsRom(Function) , oC_ErrorCode_WrongAddress )
405  && ErrorCondition( InterruptHandler == NULL , oC_ErrorCode_InterruptHandlerAlreadySet )
406  )
407  {
408  InterruptHandler = Function;
409  errorCode = oC_ErrorCode_None;
410  }
411  }
412 
413  oC_MCS_ExitCriticalSection();
414 
415  return errorCode;
416 }
417 
418 //==========================================================================================================================================
423 //==========================================================================================================================================
424 bool oC_ETH_LLD_IsAutoPadGenerationSupported( void )
425 {
426  return true;
427 }
428 
429 //==========================================================================================================================================
434 //==========================================================================================================================================
435 bool oC_ETH_LLD_IsAutoCalculateCrcSupported( void )
436 {
437  return true;
438 }
439 
440 //==========================================================================================================================================
445 //==========================================================================================================================================
446 oC_ErrorCode_t oC_ETH_LLD_InitializeMac( const oC_ETH_LLD_Config_t * Config , const oC_ETH_LLD_PHY_ChipInfo_t * ChipInfo , oC_ETH_LLD_Result_t * outResult )
447 {
448  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
449 
450  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_ETH_LLD))
451  {
452  if(
453  ErrorCondition( IsRam(Config) || IsRom(Config) , oC_ErrorCode_WrongConfigAddress )
454  && ErrorCondition( IsRam(ChipInfo) || IsRom(ChipInfo) , oC_ErrorCode_WrongAddress )
455  && ErrorCondition( IsRam(outResult) , oC_ErrorCode_OutputAddressNotInRAM )
456  && ErrorCode( CheckPhyCommunicationInterface( ChipInfo->CommunicationInterface ))
457  && ErrorCode( ConnectPins( Config, ChipInfo->CommunicationInterface, outResult ))
458  && ErrorCode( EnableClock( ChipInfo->CommunicationInterface ))
459  )
460  {
461  outResult->RxData.Alignment = 16;
462  outResult->RxData.DescriptorSize = sizeof(struct Descriptor_t) + sizeof(oC_ETH_LLD_Frame_t);
463  outResult->RxData.RingSize = DESCRIPTOR_LIST_SIZE;
464  outResult->TxData.Alignment = 16;
465  outResult->TxData.DescriptorSize = sizeof(struct Descriptor_t) + sizeof(oC_ETH_LLD_Frame_t);
466  outResult->TxData.RingSize = DESCRIPTOR_LIST_SIZE;
467  outResult->NumberOfMacAddresses = 4;
468  ConfiguredPhyCommunicationInterface = ChipInfo->CommunicationInterface;
469 
470  //==============================================================================================================================
471  /* *
472  * MAC Initialization in registers *
473  * */
474  //==============================================================================================================================
475  oC_RegisterType_ETH_MACCR_t maccr = { .Value = ETH_MACCR->Value };
476 
477  maccr.WD = 0; /* Watchdog enabled */
478  maccr.JD = 0; /* Jabber enabled */
479  maccr.IFG = 0; /* Interframe gap 96 bit times */
480  maccr.CSD = 0; /* Carrier Sense enabled */
481  maccr.FES = Config->BaudRate == oC_BaudRate_MBd(100) ? 1 : 0; /* Fast Ethernet Speed */
482  maccr.ROD = 0; /* Receive own disabled */
483  maccr.LM = 0; /* Loopback mode disabled */
484  maccr.DM = Config->OperationMode == oC_ETH_LLD_OperationMode_FullDuplex ? 1 : 0; /* Duplex Mode */
485  maccr.IPCO = 0; /* IPv4 checksum offload (0 disabled - 1 enabled) */
486  maccr.RD = 0; /* Retry disabled */
487  maccr.APCS = 0; /* Automatic pad/CRC stripping - pass all incoming frames unmodified */
488  maccr.BL = 0; /* Back-off limit - 10 */
489  maccr.DC = 0; /* Deferral check disabled */
490 
491  ETH_MACCR->Value = maccr.Value;
492 
493  /* Wait until the operation is complete and write it again */
494  maccr.Value = ETH_MACCR->Value;
495  oC_MCS_Delay(50);
496  ETH_MACCR->Value = maccr.Value;
497 
498  /* MACFFR configuration */
499  oC_RegisterType_ETH_MACFFR_t macffr = { .Value = ETH_MACFFR->Value };
500 
501  macffr.RA = 0; /* Receive all - also frames that are not for us (not for our MAC address) (0-disabled, 1 - enabled)*/
502  macffr.SAF = 0; /* Source address filter disabled */
503  macffr.PCF = 0x1; /* Prevent control frames */
504  macffr.BFD = 0; /* Broadcast frames enabled */
505  macffr.DAIF = 0; /* Destination address filter not inverted */
506  macffr.PM = 0; /* Promiscuous mode - receive all frames regardless of their destination or source address */
507  macffr.PAM = 1; /* All multicast frames passed */
508 
509  /* Wait until the operation is complete and write it again */
510  macffr.Value = ETH_MACFFR->Value;
511  oC_MCS_Delay(50);
512  ETH_MACFFR->Value = macffr.Value;
513 
514  errorCode = oC_ErrorCode_None;
515  }
516  }
517 
518  return errorCode;
519 }
520 
521 //==========================================================================================================================================
526 //==========================================================================================================================================
527 oC_ErrorCode_t oC_ETH_LLD_ReleaseMac( const oC_ETH_LLD_Config_t * Config , const oC_ETH_LLD_PHY_ChipInfo_t * ChipInfo , oC_ETH_LLD_Result_t * Result )
528 {
529  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
530 
531  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_ETH_LLD))
532  {
533  if(
534  ErrorCondition( IsRam(Config) || IsRom(Config) , oC_ErrorCode_WrongConfigAddress )
535  && ErrorCondition( IsRam(ChipInfo) , oC_ErrorCode_WrongAddress )
536  && ErrorCondition( IsRam(Result) , oC_ErrorCode_WrongAddress )
537  && oC_AssignErrorCode( &errorCode , DisconnectPins(Result->ConnectedPins, oC_ARRAY_SIZE(Result->ConnectedPins) ) )
538  && oC_AssignErrorCode( &errorCode , DisableClock() )
539  )
540  {
541  memset(Result,0,sizeof(oC_ETH_LLD_Result_t));
542 
543  TxDescriptor = NULL;
544  RxDescriptor = NULL;
545 
546  errorCode = oC_ErrorCode_None;
547  }
548  }
549 
550  return errorCode;
551 }
552 
553 
554 //==========================================================================================================================================
559 //==========================================================================================================================================
560 oC_ErrorCode_t oC_ETH_LLD_ReadPhyRegister( oC_ETH_LLD_PHY_Address_t PhyAddress , oC_ETH_LLD_PHY_RegisterAddress_t RegisterAddress , uint32_t * outValue )
561 {
562  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
563 
564  if(oC_Module_TurnOnVerification(&errorCode, oC_Module_ETH_LLD))
565  {
566  if(
567  ErrorCondition( oC_Machine_IsChannelPoweredOn(ETH_Channel) , oC_ErrorCode_MacNotInitialized )
568  && ErrorCondition( PhyAddress <= MAX_PHY_ADDRESS , oC_ErrorCode_PhyAddressNotCorrect )
569  && ErrorCondition( RegisterAddress <= MAX_PHY_REGISTER_ADDRESS , oC_ErrorCode_RegisterAddressNotCorrect )
570  && ErrorCondition( IsRam(outValue) , oC_ErrorCode_OutputAddressNotInRAM )
571  )
572  {
573  oC_MCS_EnterCriticalSection();
574 
575  oC_RegisterType_ETH_MACMIIAR_t macMiiAr = { .Value = ETH_MACMIIAR->Value };
576  oC_Time_t time = 0;
577 
578  macMiiAr.MB = 1;
579  macMiiAr.MW = 0;
580  macMiiAr.MR = RegisterAddress;
581  macMiiAr.PA = PhyAddress;
582 
583  ETH_MACMIIAR->Value = macMiiAr.Value;
584 
585  while(ETH_MACMIIAR->MB == 1 && time < TIMEOUT)
586  {
587  time += ms(1);
588  oC_CLOCK_LLD_DelayForMicroseconds(1000);
589  }
590 
591  if(ETH_MACMIIAR->MB == 0)
592  {
593  *outValue = ETH_MACMIIDR->Value;
594  errorCode = oC_ErrorCode_None;
595  }
596  else
597  {
598  errorCode = oC_ErrorCode_Timeout;
599  }
600 
601  oC_MCS_ExitCriticalSection();
602 
603  }
604  }
605 
606  return errorCode;
607 }
608 
609 //==========================================================================================================================================
614 //==========================================================================================================================================
615 oC_ErrorCode_t oC_ETH_LLD_WritePhyRegister( oC_ETH_LLD_PHY_Address_t PhyAddress , oC_ETH_LLD_PHY_RegisterAddress_t RegisterAddress , uint32_t Value )
616 {
617  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
618 
619  if(oC_Module_TurnOnVerification(&errorCode, oC_Module_ETH_LLD))
620  {
621  if(
622  ErrorCondition( oC_Machine_IsChannelPoweredOn(ETH_Channel) , oC_ErrorCode_MacNotInitialized )
623  && ErrorCondition( PhyAddress <= MAX_PHY_ADDRESS , oC_ErrorCode_PhyAddressNotCorrect )
624  && ErrorCondition( RegisterAddress <= MAX_PHY_REGISTER_ADDRESS , oC_ErrorCode_RegisterAddressNotCorrect )
625  && ErrorCondition( Value <= MAX_PHY_REGISTER_DATA_VALUE , oC_ErrorCode_ValueTooBig )
626  )
627  {
628  oC_MCS_EnterCriticalSection();
629 
630  oC_RegisterType_ETH_MACMIIAR_t macMiiAr = { .Value = ETH_MACMIIAR->Value };
631  oC_Time_t time = 0;
632 
633  macMiiAr.MB = 1;
634  macMiiAr.MW = 1;
635  macMiiAr.MR = RegisterAddress;
636  macMiiAr.PA = PhyAddress;
637 
638  ETH_MACMIIDR->Value = Value;
639  ETH_MACMIIAR->Value = macMiiAr.Value;
640 
641  while(ETH_MACMIIAR->MB == 1 && time < TIMEOUT)
642  {
643  time += ms(1);
644  oC_CLOCK_LLD_DelayForMicroseconds(1000);
645  }
646 
647  if(ETH_MACMIIAR->MB == 0)
648  {
649  errorCode = oC_ErrorCode_None;
650  }
651  else
652  {
653  errorCode = oC_ErrorCode_Timeout;
654  }
655 
656  oC_MCS_ExitCriticalSection();
657 
658  }
659  }
660 
661  return errorCode;
662 }
663 
664 //==========================================================================================================================================
669 //==========================================================================================================================================
670 oC_ErrorCode_t oC_ETH_LLD_SetMacLoopback( bool Enabled )
671 {
672  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
673 
674  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_ETH_LLD))
675  {
676  if(ErrorCondition( oC_Machine_IsChannelPoweredOn(ETH_Channel) , oC_ErrorCode_MacNotInitialized ))
677  {
678  ETH_MACCR->LM = Enabled ? 1 : 0;
679  errorCode = oC_ErrorCode_None;
680  }
681  }
682 
683  return errorCode;
684 }
685 
686 //==========================================================================================================================================
691 //==========================================================================================================================================
692 oC_ErrorCode_t oC_ETH_LLD_InitializeDescriptors( oC_ETH_LLD_Result_t * Result , const oC_ETH_LLD_Config_t * Config , oC_ETH_LLD_Descriptor_t Tx , oC_ETH_LLD_Descriptor_t Rx )
693 {
694  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
695 
696  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_ETH_LLD))
697  {
698  if(
699  ErrorCondition( IsRam(Config) || IsRom(Config) , oC_ErrorCode_WrongConfigAddress )
700  && ErrorCondition( IsDma(Tx) , oC_ErrorCode_NotDmaAddress )
701  && ErrorCondition( IsDma(Rx) , oC_ErrorCode_NotDmaAddress )
702  && ErrorCondition( IsRam(Result) , oC_ErrorCode_OutputAddressNotInRAM )
703  )
704  {
705  oC_ETH_LLD_Frame_t* txFramesArray = (oC_ETH_LLD_Frame_t*)&Tx[Result->TxData.RingSize];
706  oC_ETH_LLD_Frame_t* rxFramesArray = (oC_ETH_LLD_Frame_t*)&Rx[Result->RxData.RingSize];
707 
708  TxDescriptor = Tx;
709  RxDescriptor = Rx;
710 
711  oC_STATIC_ASSERT( (sizeof(struct Descriptor_t) % (sizeof(uint32_t) * 4 )) == 0 , "Size of descriptor is not multiple of 4 words!" );
712 
713  /* Setting address of Rx and Tx descriptors list */
714  ETH_DMATDLAR->Value = (uint32_t)TxDescriptor;
715  ETH_DMARDLAR->Value = (uint32_t)RxDescriptor;
716 
717  for( uint32_t i = 0 ; i < DESCRIPTOR_LIST_SIZE ; i++ )
718  {
719  Tx[i].Tx0.OWN = 0;
720  Tx[i].Tx0.TCH = 1;
721  Rx[i].Rx0.OWN = 1;
722  Rx[i].Rx1.RCH = 1;
723  Rx[i].Rx1.DIC = 0;
724 
725  Tx[i].Tx1.Buffer1ByteCount = 1524;
726  Rx[i].Rx1.RBS = 1524;
727 
728  Tx[i].Frame = &txFramesArray[i];
729  Rx[i].Frame = &rxFramesArray[i];
730 
731  if(i < (DESCRIPTOR_LIST_SIZE - 1))
732  {
733  Tx[i].NextDescriptorAddress = &Tx[i+1];
734  Rx[i].NextDescriptorAddress = &Rx[i+1];
735 
736  }
737  else
738  {
739  Tx[i].NextDescriptorAddress = &Tx[0];
740  Rx[i].NextDescriptorAddress = &Rx[0];
741  }
742  }
743 
744  Result->TxData.NextDescriptor = &Tx[0];
745  Result->TxData.SegmentStarted = false;
746  Result->RxData.NextDescriptor = &Rx[0];
747  Result->RxData.SegmentStarted = false;
748  errorCode = oC_ErrorCode_None;
749  }
750  }
751 
752  return errorCode;
753 }
754 
755 //==========================================================================================================================================
760 //==========================================================================================================================================
761 oC_ErrorCode_t oC_ETH_LLD_InitializeDma( oC_ETH_LLD_Result_t * Result , const oC_ETH_LLD_Config_t * Config , oC_ETH_LLD_Descriptor_t Tx , oC_ETH_LLD_Descriptor_t Rx )
762 {
763  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
764 
765  if(oC_Module_TurnOnVerification(&errorCode, oC_Module_ETH_LLD))
766  {
767  if(
768  ErrorCondition( IsRam(Result) , oC_ErrorCode_OutputAddressNotInRAM )
769  && ErrorCondition( IsRam(Config) || IsRom(Config) , oC_ErrorCode_WrongAddress )
770  && ErrorCondition( IsDma(Tx) && IsDma(Rx) , oC_ErrorCode_OutputAddressNotInRAM )
771  )
772  {
773  oC_RegisterType_ETH_DMABMR_t dmabmr = { .Value = ETH_DMABMR->Value };
774  oC_RegisterType_ETH_DMAOMR_t dmaomr = { .Value = ETH_DMAOMR->Value };
775 
776  dmaomr.DTCEFD = 0; /* Dropping of TCP/IP checksum error frames enable */
777  dmaomr.RSF = 1; /* Receive store and forward */
778  dmaomr.DFRF = 0; /* Enable flushing of received frames */
779  dmaomr.TSF = 1; /* Transmit store and forward enable */
780  dmaomr.TTC = 0; /* Transmit threshold control - 64Bytes */
781  dmaomr.FEF = 0; /* Forward Error Frames - disable */
782  dmaomr.FUGF = 0; /* Forward undersized good frames - disable */
783  dmaomr.RTC = 0; /* Receive threshold control - 64Bytes */
784  dmaomr.OSF = 1; /* Operate on second frame to transmit even before of status of the first frame */
785 
786  ETH_DMAOMR->Value = dmaomr.Value;
787 
788  /* Wait until the operation is complete and write it again */
789  dmaomr.Value = ETH_DMAOMR->Value;
790  oC_MCS_Delay(50);
791  ETH_DMAOMR->Value = dmaomr.Value;
792 
793  dmabmr.AAB = 1; /* Address-Aligned beats */
794  dmabmr.FB = 1; /* Fixed burst */
795  dmabmr.RDP = 32; /* Rx DMA PBL - Maximum number of beats to be transferred in one RxDMA transaction */
796  dmabmr.PBL = 32; /* Tx DMA PBL - Maximum number of betas to be transferred in one TxDMA transaction */
797  dmabmr.EDFE = 0; /* Enhanced descriptor format disabled TODO: make sure, that it can be disabled */
798  dmabmr.DSL = 0; /* Descriptor skip length - number of words to skip between to unchained descriptors */
799  dmabmr.DA = 0; /* DMA Arbitration - priority given as ETH_DMABMR->PM */
800  dmabmr.PM = 0; /* Rx Tx priority ratio - 1:1 */
801  dmabmr.USP = 1; /* Use separate PBL - enabled. This means, that PBL is separately configured for Rx and Tx in PBL and RDP fields */
802 
803  ETH_DMABMR->Value = dmabmr.Value;
804 
805  /* Wait until the operation is complete and write it again */
806  dmabmr.Value = ETH_DMABMR->Value;
807  oC_MCS_Delay(50);
808  ETH_DMABMR->Value = dmabmr.Value;
809 
810  /* Enable Rx interrupt */
811  ETH_DMAIER->NISE = 1; /* Normal Interrupt Summary Enabled */
812  ETH_DMAIER->RIE = 1; /* Receive Interrupt Enabled */
813  ETH_DMAIER->TIE = 1; /* Transmit Interrupt Enabled */
814 
815  errorCode = oC_ErrorCode_None;
816  }
817  }
818 
819  return errorCode;
820 }
821 
822 //==========================================================================================================================================
827 //==========================================================================================================================================
828 oC_ErrorCode_t oC_ETH_LLD_SendFrame( oC_ETH_LLD_Result_t * Result , const oC_ETH_LLD_MacAddress_t Source, const oC_ETH_LLD_MacAddress_t Destination, const void * Data , uint16_t Size , oC_ETH_LLD_FrameSegment_t FrameSegment , uint16_t EtherType )
829 {
830  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
831 
832  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_ETH_LLD))
833  {
834  if(
835  ErrorCondition( IsRam(Source) || IsRom(Source) , oC_ErrorCode_WrongAddress )
836  && ErrorCondition( IsRam(Destination) || IsRom(Destination) , oC_ErrorCode_WrongAddress )
837  && ErrorCondition( IsRam(Data) || IsRom(Data) , oC_ErrorCode_WrongAddress )
838  && ErrorCondition( IsRam(Result) , oC_ErrorCode_OutputAddressNotInRAM )
839  && ErrorCondition( Size > 0 , oC_ErrorCode_SizeNotCorrect )
840  && ErrorCondition( Size <= oC_ETH_LLD_ETHERNET_MTU , oC_ErrorCode_FrameWidthNotSupported )
841  && ErrorCondition( IsDma(TxDescriptor) , oC_ErrorCode_DescriptorListNotInitialized )
842  && ErrorCondition( IsDma(Result->TxData.NextDescriptor) , oC_ErrorCode_InternalDataAreDamaged )
843  && ErrorCondition( FrameSegment < oC_ETH_LLD_FrameSegment_NumberOfFrameSegments , oC_ErrorCode_SegmentTypeNotSupported )
844  && ErrorCondition( EtherType > 0 , oC_ErrorCode_FrameTypeNotSupported )
845  )
846  {
847  oC_MCS_EnterCriticalSection();
848  oC_ETH_LLD_Descriptor_t descriptor = Result->TxData.NextDescriptor->Tx0.OWN == 0 ? Result->TxData.NextDescriptor : NULL;
849 
850  if(
851  ErrorCondition( descriptor != NULL , oC_ErrorCode_NoFreeSlots )
852  && ErrorCondition( Result->TxData.SegmentStarted == false || FrameSegment > oC_ETH_LLD_FrameSegment_First , oC_ErrorCode_ModuleIsBusy )
853  )
854  {
855  uint8_t * destination = (uint8_t*)descriptor->Frame->Data;
856  const uint8_t * source = Data;
857 
858  /* Cleaning the frame */
859  memset( descriptor->Frame , 0 , sizeof(oC_ETH_LLD_Frame_t) );
860 
861  if(FrameSegment & oC_ETH_LLD_FrameSegment_First)
862  {
863  memcpy( descriptor->Frame->SourceAddress , Source , sizeof(oC_ETH_LLD_MacAddress_t));
864  memcpy( descriptor->Frame->DestinationAddress , Destination , sizeof(oC_ETH_LLD_MacAddress_t));
865 
866  descriptor->Frame->DataLengthEtherType = EtherType;
867  descriptor->Tx1.Buffer1ByteCount = Size + 14;
868 
869  }
870  else
871  {
872  descriptor->Tx1.Buffer1ByteCount = Size;
873  destination = (uint8_t*)descriptor->Frame;
874  }
875 
876  /* This is workaround for a problem with copying data from the external ram to the internal RAM memory. *
877  * When the 'memcpy' is used for this operation it causes a hard fault. I am not sure why, probably it can be *
878  * related with memory accessing time. It happens in the receive frame function, but probably it will occur *
879  * also here. Just in case I'm adding it here also. */
880  for(uint32_t offset = 0 ; offset < Size ; offset ++)
881  {
882  destination[offset] = source[offset];
883  }
884 
885  descriptor->Tx0.CIC = 0x0;
886 
887  if(FrameSegment == oC_ETH_LLD_FrameSegment_First)
888  {
889  descriptor->Tx0.LS = 0;
890  descriptor->Tx0.FS = 1;
891  }
892  else if(FrameSegment == oC_ETH_LLD_FrameSegment_Last)
893  {
894  descriptor->Tx0.LS = 1;
895  descriptor->Tx0.FS = 0;
896  }
897  else
898  {
899  descriptor->Tx0.LS = 1;
900  descriptor->Tx0.FS = 1;
901  }
902 
903  descriptor->Tx0.OWN = 1;
904 
905  descriptor->Tx0.DC = 0;
906  descriptor->Tx0.DP = 0;
907  Result->TxData.NextDescriptor = Result->TxData.NextDescriptor->NextDescriptorAddress;
908 
909  /* If the transfer is suspended */
910  if(DmaStatus->TransmitProcessState == TransmitProcessState_SuspendedTransmitDescriptorUnavailable)
911  {
912  ETH_DMASR->TBUS = 1; /* Clear status */
913  ETH_DMATPDR->Value = 0xFFFF; /* Resume transmission */
914  }
915 
916  Result->TxData.NextDescriptor = descriptor->NextDescriptorAddress;
917  errorCode = oC_ErrorCode_None;
918  }
919  oC_MCS_ExitCriticalSection();
920  }
921  }
922 
923  return errorCode;
924 }
925 
926 //==========================================================================================================================================
931 //==========================================================================================================================================
932 oC_ErrorCode_t oC_ETH_LLD_ReceiveFrame( oC_ETH_LLD_Result_t * Result , oC_ETH_LLD_MacAddress_t outSource, oC_ETH_LLD_MacAddress_t outDestination, void * Data , uint16_t * Size , oC_ETH_LLD_FrameSegment_t * outFrameSegment , uint16_t * outEtherType )
933 {
934  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
935 
936  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_ETH_LLD))
937  {
938  if(
939  ErrorCondition( IsRam(Result) , oC_ErrorCode_OutputAddressNotInRAM )
940  && ErrorCondition( IsRam(outDestination) , oC_ErrorCode_OutputAddressNotInRAM )
941  && ErrorCondition( IsRam(Data) , oC_ErrorCode_OutputAddressNotInRAM )
942  && ErrorCondition( IsRam(Size) , oC_ErrorCode_OutputAddressNotInRAM )
943  && ErrorCondition( (*Size) > 0 , oC_ErrorCode_SizeNotCorrect )
944  && ErrorCondition( IsRam(outFrameSegment) , oC_ErrorCode_OutputAddressNotInRAM )
945  && ErrorCondition( IsRam(outEtherType) , oC_ErrorCode_OutputAddressNotInRAM )
946  && ErrorCondition( IsDma(RxDescriptor) , oC_ErrorCode_DescriptorListNotInitialized )
947  && ErrorCondition( IsDma(Result->RxData.NextDescriptor) , oC_ErrorCode_InternalDataAreDamaged )
948  && ErrorCondition( IsRam(Result->RxData.NextDescriptor->Frame) ||
949  IsDma(Result->RxData.NextDescriptor->Frame) , oC_ErrorCode_InternalDataAreDamaged )
950  )
951  {
952  oC_ETH_LLD_Descriptor_t descriptor = Result->RxData.NextDescriptor;
953  uint16_t dataSize = descriptor->Rx0.FL - sizeof(uint32_t);
954 
955  oC_MCS_EnterCriticalSection();
956  if(
957  ErrorCondition( descriptor->Rx0.OWN == 0 , oC_ErrorCode_DataNotAvailable )
958  && ErrorCondition( dataSize <= (*Size) , oC_ErrorCode_OutputBufferTooSmall )
959  )
960  {
961  uint8_t * destination = Data;
962  const uint8_t * source = (const uint8_t*)descriptor->Frame->Data;
963 
964  *Size = dataSize;
965  descriptor->Rx0.OWN = 1;
966  *outEtherType = descriptor->Frame->DataLengthEtherType;
967 
968  memcpy(outSource , descriptor->Frame->SourceAddress , sizeof(oC_ETH_LLD_MacAddress_t) );
969  memcpy(outDestination , descriptor->Frame->DestinationAddress , sizeof(oC_ETH_LLD_MacAddress_t) );
970 
971  /* This is workaround for a problem with copying data from the ram (also internal) to the external RAM memory. *
972  * When the 'memcpy' is used for this operation it causes a hard fault. I am not sure why, probably it can be *
973  * related with memory accessing time */
974  for(uint32_t offset = 0 ; offset < dataSize ; offset ++)
975  {
976  destination[offset] = source[offset];
977  }
978 
979  if(Result->RxData.SegmentStarted == false && descriptor->Rx0.FS == 1 && descriptor->Rx0.LS == 1)
980  {
981  *outFrameSegment = oC_ETH_LLD_FrameSegment_Single;
982  errorCode = oC_ErrorCode_None;
983  }
984  else if(Result->RxData.SegmentStarted == false && descriptor->Rx0.FS == 1 && descriptor->Rx0.LS == 0)
985  {
986  Result->RxData.SegmentStarted = true;
987  *outFrameSegment = oC_ETH_LLD_FrameSegment_First;
988  errorCode = oC_ErrorCode_None;
989  }
990  else if(Result->RxData.SegmentStarted == true && descriptor->Rx0.FS == 0 && descriptor->Rx0.LS == 1)
991  {
992  Result->RxData.SegmentStarted = false;
993  *outFrameSegment = oC_ETH_LLD_FrameSegment_Last;
994  errorCode = oC_ErrorCode_None;
995  }
996  else if(Result->RxData.SegmentStarted == true && descriptor->Rx0.FS == 0 && descriptor->Rx0.LS == 0)
997  {
998  *outFrameSegment = oC_ETH_LLD_FrameSegment_Middle;
999  errorCode = oC_ErrorCode_None;
1000  }
1001  else
1002  {
1003  errorCode = oC_ErrorCode_InternalDataAreDamaged;
1004  }
1005 
1006  Result->RxData.NextDescriptor = (void*)descriptor->NextDescriptorAddress;
1007 
1008  /* If the transfer is suspended */
1009  if(DmaStatus->ReceiveProcessState == ReceiveProcessState_SuspendedReceiveDescriptorUnavailable)
1010  {
1011  ETH_DMASR->RBUS = 1; /* Clear status */
1012  ETH_DMATPDR->Value = 0xFFFF; /* Resume transmission */
1013  }
1014  }
1015  oC_MCS_ExitCriticalSection();
1016  }
1017  }
1018 
1019  return errorCode;
1020 }
1021 
1022 //==========================================================================================================================================
1027 //==========================================================================================================================================
1028 oC_ErrorCode_t oC_ETH_LLD_Start( const oC_ETH_LLD_Config_t * Config )
1029 {
1030  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1031 
1032  if(oC_Module_TurnOnVerification(&errorCode, oC_Module_ETH_LLD))
1033  {
1034  if(
1035  ErrorCondition( IsRam(Config) || IsRom(Config) , oC_ErrorCode_WrongAddress )
1036  && ErrorCondition( Config->BaudRate == oC_BaudRate_MBd(10) || Config->BaudRate == oC_BaudRate_MBd(100) , oC_ErrorCode_BaudRateNotSupported )
1037  && ErrorCondition( Config->OperationMode == oC_ETH_LLD_OperationMode_FullDuplex
1038  || Config->OperationMode == oC_ETH_LLD_OperationMode_HalfDuplex , oC_ErrorCode_OperationModeNotCorrect )
1039  && ErrorCondition( oC_Channel_EnableInterruptFunction(oC_Channel_ETH, oC_InterruptType_PeripheralInterrupt) , oC_ErrorCode_CannotEnableInterrupt )
1040  )
1041  {
1042  oC_RegisterType_ETH_MACCR_t maccr = { .Value = ETH_MACCR->Value };
1043  oC_RegisterType_ETH_MACFFR_t macffr = { .Value = ETH_MACFFR->Value };
1044  oC_RegisterType_ETH_DMAOMR_t dmaomr = { .Value = ETH_DMAOMR->Value };
1045 
1046  maccr.TE = 1;
1047 
1048  ETH_MACCR->Value = maccr.Value;
1049  maccr.Value = ETH_MACCR->Value;
1050  oC_MCS_Delay(50);
1051  ETH_MACCR->Value = maccr.Value;
1052 
1053  maccr.RE = 1;
1054 
1055  ETH_MACCR->Value = maccr.Value;
1056  maccr.Value = ETH_MACCR->Value;
1057  oC_MCS_Delay(50);
1058  ETH_MACCR->Value = maccr.Value;
1059 
1060  dmaomr.FTF = 1;
1061 
1062  ETH_DMAOMR->Value = dmaomr.Value;
1063  dmaomr.Value = ETH_DMAOMR->Value;
1064  oC_MCS_Delay(50);
1065  ETH_DMAOMR->Value = dmaomr.Value;
1066 
1067  dmaomr.ST = 1;
1068 
1069  ETH_DMAOMR->Value = dmaomr.Value;
1070  dmaomr.Value = ETH_DMAOMR->Value;
1071  oC_MCS_Delay(50);
1072  ETH_DMAOMR->Value = dmaomr.Value;
1073 
1074  dmaomr.SR = 1;
1075 
1076  ETH_DMAOMR->Value = dmaomr.Value;
1077  dmaomr.Value = ETH_DMAOMR->Value;
1078  oC_MCS_Delay(50);
1079  ETH_DMAOMR->Value = dmaomr.Value;
1080 
1081  macffr.RA = 1;
1082 
1083  ETH_MACFFR->Value = macffr.Value;
1084  macffr.Value = ETH_MACFFR->Value;
1085  oC_MCS_Delay(50);
1086  ETH_MACFFR->Value = macffr.Value;
1087 
1088  errorCode = oC_ErrorCode_None;
1089  }
1090  }
1091 
1092  return errorCode;
1093 }
1094 
1095 //==========================================================================================================================================
1100 //==========================================================================================================================================
1101 oC_ErrorCode_t oC_ETH_LLD_SetMacAddress( oC_ETH_LLD_Result_t * Result , uint32_t MacAddressIndex, const oC_ETH_LLD_MacAddress_t Address )
1102 {
1103  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1104 
1105  if(oC_Module_TurnOnVerification( &errorCode , oC_Module_ETH_LLD ))
1106  {
1107  if(
1108  ErrorCondition( IsRam(Result) || IsRom(Result) , oC_ErrorCode_WrongAddress )
1109  && ErrorCondition( IsRam(Address) || IsRom(Address) , oC_ErrorCode_WrongAddress )
1110  && ErrorCondition( MacAddressIndex >= 0 && MacAddressIndex < 4 , oC_ErrorCode_WrongMacAddressIndex )
1111  )
1112  {
1113  switch(MacAddressIndex)
1114  {
1115  case 0:
1116  ETH_MACA0LR->MACA0LR = (((uint32_t)Address[0]) << 0)
1117  | (((uint32_t)Address[1]) << 8)
1118  | (((uint32_t)Address[2]) << 16)
1119  | (((uint32_t)Address[3]) << 24);
1120  ETH_MACA0HR->MACA0H = (((uint32_t)Address[4]) << 0)
1121  | (((uint32_t)Address[5]) << 8);
1122  errorCode = oC_ErrorCode_None;
1123  break;
1124  case 1:
1125  ETH_MACA1LR->MACA1LR = (((uint32_t)Address[0]) << 0)
1126  | (((uint32_t)Address[1]) << 8)
1127  | (((uint32_t)Address[2]) << 16)
1128  | (((uint32_t)Address[3]) << 24);
1129  ETH_MACA1HR->MACA1H = (((uint32_t)Address[4]) << 0)
1130  | (((uint32_t)Address[5]) << 8);
1131  errorCode = oC_ErrorCode_None;
1132  break;
1133  case 2:
1134  ETH_MACA2LR->MACA2LR = (((uint32_t)Address[0]) << 0)
1135  | (((uint32_t)Address[1]) << 8)
1136  | (((uint32_t)Address[2]) << 16)
1137  | (((uint32_t)Address[3]) << 24);
1138  ETH_MACA2HR->MACA2H = (((uint32_t)Address[4]) << 0)
1139  | (((uint32_t)Address[5]) << 8);
1140  errorCode = oC_ErrorCode_None;
1141  break;
1142  case 3:
1143  ETH_MACA3LR->MACA3LR = (((uint32_t)Address[0]) << 0)
1144  | (((uint32_t)Address[1]) << 8)
1145  | (((uint32_t)Address[2]) << 16)
1146  | (((uint32_t)Address[3]) << 24);
1147  ETH_MACA3HR->MACA3H = (((uint32_t)Address[4]) << 0)
1148  | (((uint32_t)Address[5]) << 8);
1149  errorCode = oC_ErrorCode_None;
1150  break;
1151  default:
1152  errorCode = oC_ErrorCode_WrongMacAddressIndex;
1153  break;
1154  }
1155  }
1156  }
1157 
1158  return errorCode;
1159 }
1160 
1161 //==========================================================================================================================================
1166 //==========================================================================================================================================
1167 oC_ErrorCode_t oC_ETH_LLD_ReadMacAddress( oC_ETH_LLD_Result_t * Result , uint32_t MacAddressIndex, oC_ETH_LLD_MacAddress_t outAddress )
1168 {
1169  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1170 
1171  if(oC_Module_TurnOnVerification( &errorCode , oC_Module_ETH_LLD ))
1172  {
1173  if(
1174  ErrorCondition( IsRam(Result) || IsRom(Result) , oC_ErrorCode_WrongAddress )
1175  && ErrorCondition( IsRam(outAddress) , oC_ErrorCode_WrongAddress )
1176  && ErrorCondition( MacAddressIndex >= 0 && MacAddressIndex < 4 , oC_ErrorCode_WrongMacAddressIndex )
1177  )
1178  {
1179  switch(MacAddressIndex)
1180  {
1181  case 0:
1182  outAddress[0] = (uint8_t)(ETH_MACA0LR->MACA0LR >> 0);
1183  outAddress[1] = (uint8_t)(ETH_MACA0LR->MACA0LR >> 8);
1184  outAddress[2] = (uint8_t)(ETH_MACA0LR->MACA0LR >> 16);
1185  outAddress[3] = (uint8_t)(ETH_MACA0LR->MACA0LR >> 24);
1186  outAddress[4] = (uint8_t)(ETH_MACA0HR->MACA0H >> 0);
1187  outAddress[5] = (uint8_t)(ETH_MACA0HR->MACA0H >> 8);
1188  errorCode = oC_ErrorCode_None;
1189  break;
1190  case 1:
1191  outAddress[0] = (uint8_t)(ETH_MACA1LR->MACA1LR >> 0);
1192  outAddress[1] = (uint8_t)(ETH_MACA1LR->MACA1LR >> 8);
1193  outAddress[2] = (uint8_t)(ETH_MACA1LR->MACA1LR >> 16);
1194  outAddress[3] = (uint8_t)(ETH_MACA1LR->MACA1LR >> 24);
1195  outAddress[4] = (uint8_t)(ETH_MACA1HR->MACA1H >> 0);
1196  outAddress[5] = (uint8_t)(ETH_MACA1HR->MACA1H >> 8);
1197  errorCode = oC_ErrorCode_None;
1198  break;
1199  case 2:
1200  outAddress[0] = (uint8_t)(ETH_MACA2LR->MACA2LR >> 0);
1201  outAddress[1] = (uint8_t)(ETH_MACA2LR->MACA2LR >> 8);
1202  outAddress[2] = (uint8_t)(ETH_MACA2LR->MACA2LR >> 16);
1203  outAddress[3] = (uint8_t)(ETH_MACA2LR->MACA2LR >> 24);
1204  outAddress[4] = (uint8_t)(ETH_MACA2HR->MACA2H >> 0);
1205  outAddress[5] = (uint8_t)(ETH_MACA2HR->MACA2H >> 8);
1206  errorCode = oC_ErrorCode_None;
1207  break;
1208  case 3:
1209  outAddress[0] = (uint8_t)(ETH_MACA3LR->MACA3LR >> 0);
1210  outAddress[1] = (uint8_t)(ETH_MACA3LR->MACA3LR >> 8);
1211  outAddress[2] = (uint8_t)(ETH_MACA3LR->MACA3LR >> 16);
1212  outAddress[3] = (uint8_t)(ETH_MACA3LR->MACA3LR >> 24);
1213  outAddress[4] = (uint8_t)(ETH_MACA3HR->MACA3H >> 0);
1214  outAddress[5] = (uint8_t)(ETH_MACA3HR->MACA3H >> 8);
1215  errorCode = oC_ErrorCode_None;
1216  break;
1217  default:
1218  errorCode = oC_ErrorCode_WrongMacAddressIndex;
1219  break;
1220  }
1221  }
1222  }
1223  return errorCode;
1224 }
1225 
1226 //==========================================================================================================================================
1231 //==========================================================================================================================================
1232 bool oC_ETH_LLD_IsTransmitQueueFull( oC_ETH_LLD_Result_t * Result )
1233 {
1234  bool full = false;
1235 
1236  if(oC_Module_IsTurnedOn(oC_Module_ETH_LLD))
1237  {
1238  oC_MCS_EnterCriticalSection();
1239  full = Result->TxData.NextDescriptor->Tx0.OWN == 1;
1240  oC_MCS_ExitCriticalSection();
1241 
1242  }
1243 
1244  return full;
1245 }
1246 
1247 //==========================================================================================================================================
1252 //==========================================================================================================================================
1253 bool oC_ETH_LLD_IsDataReadyToReceive( oC_ETH_LLD_Result_t * Result )
1254 {
1255  bool full = false;
1256 
1257  if(oC_Module_IsTurnedOn(oC_Module_ETH_LLD))
1258  {
1259  oC_MCS_EnterCriticalSection();
1260  full = Result->RxData.NextDescriptor->Rx0.OWN == 0;
1261  oC_MCS_ExitCriticalSection();
1262 
1263  }
1264 
1265  return full;
1266 }
1267 
1268 //==========================================================================================================================================
1273 //==========================================================================================================================================
1274 oC_ErrorCode_t oC_ETH_LLD_PerformDiagnostics( oC_ETH_LLD_Result_t * Result , oC_Diag_t * Diag , uint32_t * NumberOfDiags )
1275 {
1276  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1277 
1278  if(oC_Module_TurnOnVerification(&errorCode, oC_Module_ETH_LLD))
1279  {
1280  if(
1281  ErrorCondition( IsRam(Result) , oC_ErrorCode_OutputAddressNotInRAM )
1282  && ErrorCondition( IsRam(Diag) || Diag == NULL , oC_ErrorCode_OutputAddressNotInRAM )
1283  && ErrorCondition( IsRam(NumberOfDiags) , oC_ErrorCode_OutputAddressNotInRAM )
1284  && ErrorCondition( Diag == NULL || Diag->PrintFunction == NULL || IsRam(Diag->PrintFunction) || IsRom(Diag->PrintFunction) , oC_ErrorCode_WrongAddress )
1285  )
1286  {
1287  if(Diag != NULL)
1288  {
1289  errorCode = oC_Diag_PerformDiagnostics(SupportedDiagsArray,Diag,*NumberOfDiags,"ETH-LLD",Result);
1290  *NumberOfDiags = oC_Diag_GetNumberOfSupportedDiagnostics( SupportedDiagsArray );
1291  }
1292  else
1293  {
1294  *NumberOfDiags = oC_Diag_GetNumberOfSupportedDiagnostics( SupportedDiagsArray );
1295  errorCode = oC_ErrorCode_None;
1296  }
1297  }
1298  }
1299 
1300  return errorCode;
1301 }
1302 
1303 #undef _________________________________________FUNCTIONS_SECTION__________________________________________________________________________
1304 
1310 #define _________________________________________LOCAL_FUNCTIONS_SECTION____________________________________________________________________
1311 
1312 //==========================================================================================================================================
1316 //==========================================================================================================================================
1317 static oC_ErrorCode_t ConnectPins( const oC_ETH_LLD_Config_t * Config , oC_ETH_LLD_PHY_CommunicationInterface_t CommunicationInterface , oC_ETH_LLD_Result_t * outResult )
1318 {
1319  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1320  uint32_t pinIndex = 0;
1321 
1322  memset(outResult->ConnectedPins,0,sizeof(outResult->ConnectedPins));
1323 
1324  if(CommunicationInterface == oC_ETH_LLD_PHY_CommunicationInterface_MII)
1325  {
1326  if(
1327  oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.Mdc , oC_ETH_PinFunction_ETH_MDC , &outResult->ConnectedPins[pinIndex++] ) )
1328  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.Mdio , oC_ETH_PinFunction_ETH_MDIO , &outResult->ConnectedPins[pinIndex++] ) )
1329  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.Col , oC_ETH_PinFunction_ETH_MII_COL , &outResult->ConnectedPins[pinIndex++] ) )
1330  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.Crs , oC_ETH_PinFunction_ETH_MII_CRS , &outResult->ConnectedPins[pinIndex++] ) )
1331  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.RxClk , oC_ETH_PinFunction_ETH_MII_RX_CLK , &outResult->ConnectedPins[pinIndex++] ) )
1332  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.RxD0 , oC_ETH_PinFunction_ETH_MII_RXD0 , &outResult->ConnectedPins[pinIndex++] ) )
1333  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.RxD1 , oC_ETH_PinFunction_ETH_MII_RXD1 , &outResult->ConnectedPins[pinIndex++] ) )
1334  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.RxD2 , oC_ETH_PinFunction_ETH_MII_RXD2 , &outResult->ConnectedPins[pinIndex++] ) )
1335  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.RxD3 , oC_ETH_PinFunction_ETH_MII_RXD3 , &outResult->ConnectedPins[pinIndex++] ) )
1336  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.RxDv , oC_ETH_PinFunction_ETH_MII_RX_DV , &outResult->ConnectedPins[pinIndex++] ) )
1337  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.RxEr , oC_ETH_PinFunction_ETH_MII_RX_ER , &outResult->ConnectedPins[pinIndex++] ) )
1338  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.TxClk , oC_ETH_PinFunction_ETH_MII_TX_CLK , &outResult->ConnectedPins[pinIndex++] ) )
1339  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.TxD0 , oC_ETH_PinFunction_ETH_MII_TXD0 , &outResult->ConnectedPins[pinIndex++] ) )
1340  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.TxD1 , oC_ETH_PinFunction_ETH_MII_TXD1 , &outResult->ConnectedPins[pinIndex++] ) )
1341  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.TxD2 , oC_ETH_PinFunction_ETH_MII_TXD2 , &outResult->ConnectedPins[pinIndex++] ) )
1342  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.TxD3 , oC_ETH_PinFunction_ETH_MII_TXD3 , &outResult->ConnectedPins[pinIndex++] ) )
1343  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Mii.TxEn , oC_ETH_PinFunction_ETH_MII_TX_EN , &outResult->ConnectedPins[pinIndex++] ) )
1344  )
1345  {
1346  errorCode = oC_ErrorCode_None;
1347  }
1348  else
1349  {
1350  oC_SaveIfErrorOccur("ETH-LLD: Disconnect error - " , DisconnectPins(outResult->ConnectedPins, oC_ARRAY_SIZE(outResult->ConnectedPins)));
1351  }
1352  }
1353  else if(CommunicationInterface == oC_ETH_LLD_PHY_CommunicationInterface_RMII)
1354  {
1355  if(
1356  oC_AssignErrorCode(&errorCode , ConnectPin( Config->Rmii.Mdc , oC_ETH_PinFunction_ETH_MDC , &outResult->ConnectedPins[pinIndex++] ) )
1357  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Rmii.Mdio , oC_ETH_PinFunction_ETH_MDIO , &outResult->ConnectedPins[pinIndex++] ) )
1358  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Rmii.RcsDv , oC_ETH_PinFunction_ETH_RMII_CRS_DV , &outResult->ConnectedPins[pinIndex++] ) )
1359  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Rmii.RefClk , oC_ETH_PinFunction_ETH_RMII_REF_CLK , &outResult->ConnectedPins[pinIndex++] ) )
1360  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Rmii.RxD0 , oC_ETH_PinFunction_ETH_RMII_RXD0 , &outResult->ConnectedPins[pinIndex++] ) )
1361  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Rmii.RxD1 , oC_ETH_PinFunction_ETH_RMII_RXD1 , &outResult->ConnectedPins[pinIndex++] ) )
1362  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Rmii.TxD0 , oC_ETH_PinFunction_ETH_RMII_TXD0 , &outResult->ConnectedPins[pinIndex++] ) )
1363  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Rmii.TxD1 , oC_ETH_PinFunction_ETH_RMII_TXD1 , &outResult->ConnectedPins[pinIndex++] ) )
1364  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Rmii.TxEn , oC_ETH_PinFunction_ETH_RMII_TX_EN , &outResult->ConnectedPins[pinIndex++] ) )
1365  && oC_AssignErrorCode(&errorCode , ConnectPin( Config->Rmii.RxEr , oC_ETH_PinFunction_ETH_RMII_RX_ER , &outResult->ConnectedPins[pinIndex++] ) )
1366  )
1367  {
1368  errorCode = oC_ErrorCode_None;
1369  }
1370  else
1371  {
1372  oC_SaveIfErrorOccur("ETH-LLD: Disconnect error - " , DisconnectPins(outResult->ConnectedPins, oC_ARRAY_SIZE(outResult->ConnectedPins)));
1373  }
1374  }
1375  else
1376  {
1377  errorCode = oC_ErrorCode_CommunicationInterfaceNotCorrect;
1378  }
1379 
1380  return errorCode;
1381 }
1382 
1383 //==========================================================================================================================================
1387 //==========================================================================================================================================
1388 static oC_ErrorCode_t DisconnectPins( oC_Pin_t * ConnectedPins , uint16_t ArraySize )
1389 {
1390  oC_ErrorCode_t errorCode = oC_ErrorCode_None;
1391 
1392  for(uint16_t pinIndex = 0; pinIndex < ArraySize ; pinIndex++)
1393  {
1394  if(ConnectedPins[pinIndex] != oC_Pin_NotUsed)
1395  {
1396  oC_AssignErrorCode(&errorCode, DisconnectPin(ConnectedPins[pinIndex]));
1397  }
1398  }
1399 
1400  return errorCode;
1401 }
1402 
1403 //==========================================================================================================================================
1407 //==========================================================================================================================================
1408 static oC_ErrorCode_t ConnectPin( oC_Pin_t Pin , oC_PinFunction_t PinFunction , oC_Pin_t * outConnectedPinReference )
1409 {
1410  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1411 
1412  if(
1413  ErrorCondition( Pin != oC_Pin_NotUsed , oC_ErrorCode_PinNotSet )
1414  && ErrorCondition( oC_GPIO_LLD_IsPinDefined(Pin) , oC_ErrorCode_PinNotDefined )
1415  )
1416  {
1417  bool pinUsed = false;
1418  oC_ModulePinIndex_t modulePin = 0;
1419 
1420  oC_MCS_EnterCriticalSection();
1421 
1422  if(
1423  oC_AssignErrorCode( &errorCode , oC_GPIO_MSLLD_FindModulePin( Pin, ETH_Channel, PinFunction, &modulePin ) )
1424  && oC_AssignErrorCode( &errorCode , oC_GPIO_LLD_CheckIsPinUsed( Pin, &pinUsed ) )
1425  && ErrorCondition( pinUsed == false , oC_ErrorCode_PinIsUsed )
1426  && oC_AssignErrorCode( &errorCode , oC_GPIO_MSLLD_ConnectModulePin( modulePin ) )
1427  && oC_AssignErrorCode( &errorCode , oC_GPIO_LLD_SetPinsUsed( Pin ) )
1428  )
1429  {
1430  *outConnectedPinReference = Pin;
1431  errorCode = oC_ErrorCode_None;
1432  }
1433 
1434  oC_MCS_ExitCriticalSection();
1435  }
1436 
1437 
1438  return errorCode;
1439 }
1440 
1441 //==========================================================================================================================================
1445 //==========================================================================================================================================
1446 static oC_ErrorCode_t DisconnectPin( oC_Pin_t Pin )
1447 {
1448  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1449 
1450  if(
1451  oC_AssignErrorCode(&errorCode , oC_GPIO_MSLLD_DisconnectPin(Pin,0) )
1452  && oC_AssignErrorCode(&errorCode , oC_GPIO_LLD_SetPinsUnused(Pin) )
1453  )
1454  {
1455  errorCode = oC_ErrorCode_None;
1456  }
1457 
1458  return errorCode;
1459 }
1460 
1461 //==========================================================================================================================================
1465 //==========================================================================================================================================
1466 static oC_ErrorCode_t EnableClock( oC_ETH_LLD_PHY_CommunicationInterface_t CommunicationInterface )
1467 {
1468  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1469 
1470  oC_MCS_EnterCriticalSection();
1471 
1472  if(
1473  ErrorCondition( oC_Machine_SetPowerStateForChannel(ETH_Channel,oC_Power_On) , oC_ErrorCode_CannotEnableChannel )
1474  )
1475  {
1476  /* Enable Tx/Rx clocks (MAC is enabled by the enabling the ETH channel) */
1477  RCC_AHB1ENR->ETHMACRXEN = 1;
1478  RCC_AHB1ENR->ETHMACTXEN = 1;
1479 
1480  if(
1481  CommunicationInterface == oC_ETH_LLD_PHY_CommunicationInterface_MII
1482  || CommunicationInterface == oC_ETH_LLD_PHY_CommunicationInterface_RMII
1483  )
1484  {
1485  oC_RegisterType_SYSCFG_PMC_t pmc;
1486  oC_Time_t time = 0;
1487  oC_RegisterType_ETH_DMABMR_t dmabmr;
1488 
1489  pmc.Value = SYSCFG_PMC->Value;
1490  pmc.MII_RMII_SEL = CommunicationInterface == oC_ETH_LLD_PHY_CommunicationInterface_RMII;
1491  dmabmr.Value = ETH_DMABMR->Value;
1492  dmabmr.SR = 1;
1493  SYSCFG_PMC->Value = pmc.Value;
1494  ETH_DMABMR->Value = dmabmr.Value;
1495 
1496  while(ETH_DMABMR->SR == 1 && time < TIMEOUT)
1497  {
1498  time += ms(1);
1499  oC_CLOCK_LLD_DelayForMicroseconds(1000);
1500  }
1501 
1502  if(ETH_DMABMR->SR == 0)
1503  {
1504  /* These values are from machine documentation. Don't change it's order! */
1505  static const ClockRange_t ranges[] = {
1506  { .Min = MHz(60) , .Max = MHz(100) },
1507  { .Min = MHz(100) , .Max = MHz(150) },
1508  { .Min = MHz(20) , .Max = MHz(35) },
1509  { .Min = MHz(35) , .Max = MHz(60) },
1510  { .Min = MHz(150) , .Max = oC_MACHINE_MAXIMUM_FREQUENCY },
1511  };
1512  oC_Frequency_t clockFrequency = oC_CLOCK_LLD_GetClockFrequency();
1513  bool foundRange = false;
1514 
1515  for(uint8_t rangeIndex = 0; rangeIndex < oC_ARRAY_SIZE(ranges); rangeIndex++)
1516  {
1517  if(clockFrequency >= ranges[rangeIndex].Min && clockFrequency <= ranges[rangeIndex].Max)
1518  {
1519  ETH_MACMIIAR->CR = rangeIndex;
1520  foundRange = true;
1521  break;
1522  }
1523  }
1524 
1525  if(foundRange)
1526  {
1527  NumberOfConfiguredPhys++;
1528  errorCode = oC_ErrorCode_None;
1529  }
1530  else
1531  {
1532  errorCode = oC_ErrorCode_ClockConfigurationError;
1533  }
1534  }
1535  else
1536  {
1537  oC_SaveError("ETH-LLD: Cannot enable MII/RMII interface - " , errorCode);
1538  errorCode = oC_ErrorCode_Timeout;
1539  }
1540  }
1541  else
1542  {
1543  errorCode = oC_ErrorCode_CommunicationInterfaceNotCorrect;
1544  }
1545  }
1546 
1547  oC_MCS_ExitCriticalSection();
1548 
1549  return errorCode;
1550 }
1551 
1552 //==========================================================================================================================================
1556 //==========================================================================================================================================
1557 static oC_ErrorCode_t DisableClock( void )
1558 {
1559  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1560 
1561  oC_MCS_EnterCriticalSection();
1562 
1563  if(ErrorCondition( NumberOfConfiguredPhys > 0 , oC_ErrorCode_ChannelNotConfigured ))
1564  {
1565  NumberOfConfiguredPhys--;
1566 
1567  if(NumberOfConfiguredPhys == 0)
1568  {
1569  /* Disable Tx/Rx clocks */
1570  RCC_AHB1ENR->ETHMACRXEN = 0;
1571  RCC_AHB1ENR->ETHMACTXEN = 0;
1572 
1573  if(ErrorCondition(oC_Machine_SetPowerStateForChannel(ETH_Channel,oC_Power_Off) , oC_ErrorCode_CannotDisableChannel ))
1574  {
1575  errorCode = oC_ErrorCode_None;
1576  }
1577  }
1578  else
1579  {
1580  errorCode = oC_ErrorCode_None;
1581  }
1582  }
1583 
1584 
1585  oC_MCS_ExitCriticalSection();
1586 
1587  return errorCode;
1588 }
1589 
1590 //==========================================================================================================================================
1594 //==========================================================================================================================================
1595 static oC_ErrorCode_t CheckPhyCommunicationInterface( oC_ETH_LLD_PHY_CommunicationInterface_t CommunicationInterface )
1596 {
1597  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1598 
1599  if(ConfiguredPhyCommunicationInterface == oC_ETH_LLD_PHY_CommunicationInterface_None)
1600  {
1601  if(
1602  CommunicationInterface == oC_ETH_LLD_PHY_CommunicationInterface_MII
1603  || CommunicationInterface == oC_ETH_LLD_PHY_CommunicationInterface_RMII
1604  )
1605  {
1606  errorCode = oC_ErrorCode_None;
1607  }
1608  else
1609  {
1610  errorCode = oC_ErrorCode_CommunicationInterfaceNotCorrect;
1611  }
1612  }
1613  else
1614  {
1615  if(CommunicationInterface == ConfiguredPhyCommunicationInterface)
1616  {
1617  errorCode = oC_ErrorCode_None;
1618  }
1619  else
1620  {
1621  errorCode = oC_ErrorCode_OtherCommunicationInterfaceInUse;
1622  }
1623  }
1624 
1625  return errorCode;
1626 }
1627 
1628 //==========================================================================================================================================
1632 //==========================================================================================================================================
1633 static oC_ErrorCode_t PerformMacRegisterAccessTest( oC_Diag_t * Diag , void * Context )
1634 {
1635  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1636 
1637  if(
1638  ErrorCondition( IsRam(Context) , oC_ErrorCode_OutputAddressNotInRAM )
1639  )
1640  {
1641  oC_MCS_EnterCriticalSection();
1642 
1643  oC_Procedure_Begin
1644  {
1645  ETH_MACCR->LM = 1;
1646 
1647  oC_MCS_Delay(10);
1648 
1649  if(!ErrorCondition( ETH_MACCR->LM == 1 , oC_ErrorCode_CannotAccessRegister ))
1650  {
1651  Diag->ResultDescription = "Cannot access ETH_MACCR register! ETH_MACCR->LM != 1";
1652  break;
1653  }
1654 
1655  ETH_MACCR->LM = 0;
1656 
1657  oC_MCS_Delay(10);
1658 
1659  if(!ErrorCondition( ETH_MACCR->LM == 0 , oC_ErrorCode_CannotAccessRegister ))
1660  {
1661  Diag->ResultDescription = "Cannot access ETH_MACCR register! ETH_MACCR->LM != 0";
1662  break;
1663  }
1664 
1665  errorCode = oC_ErrorCode_None;
1666  }
1667  oC_Procedure_End;
1668 
1669 
1670 
1671  oC_MCS_ExitCriticalSection();
1672  }
1673 
1674  return errorCode;
1675 }
1676 
1677 #undef _________________________________________LOCAL_FUNCTIONS_SECTION____________________________________________________________________
1678 
1684 #define _________________________________________INTERRUPTS_SECTION_________________________________________________________________________
1685 
1686 //==========================================================================================================================================
1690 //==========================================================================================================================================
1691 oC_InterruptHandler(ETHERNET_MAC,PeripheralInterrupt)
1692 {
1693  oC_ETH_LLD_InterruptSource_t interruptSource = 0;
1694 
1695  if(InterruptHandler)
1696  {
1697 
1698  if(DmaStatus->ReceiveFinished)
1699  {
1700  interruptSource |= oC_ETH_LLD_InterruptSource_DataReceived;
1701  }
1702  if(DmaStatus->TransmissionFinished)
1703  {
1704  interruptSource |= oC_ETH_LLD_InterruptSource_TransmissionSlotsAvailable;
1705  }
1706 
1707  if(DmaStatus->TransmissionStopped)
1708  {
1709  interruptSource |= oC_ETH_LLD_InterruptSource_TransmitProcessStopped | oC_ETH_LLD_InterruptSource_TransmitError;
1710  }
1711 
1712  if(DmaStatus->ReceiveStopped)
1713  {
1714  interruptSource |= oC_ETH_LLD_InterruptSource_ReceiveProcessStopped | oC_ETH_LLD_InterruptSource_ReceiveError;
1715  }
1716 
1717  if(DmaStatus->ReceiveWatchdogTimeout)
1718  {
1719  interruptSource |= oC_ETH_LLD_InterruptSource_ReceiveTimeout | oC_ETH_LLD_InterruptSource_ReceiveError;
1720  }
1721 
1722  if(DmaStatus->TransmitJabberTimeout)
1723  {
1724  interruptSource |= oC_ETH_LLD_InterruptSource_TransmitJabberTimeout | oC_ETH_LLD_InterruptSource_TransmitError;
1725  }
1726 
1727  if(DmaStatus->ReceiveOverflow)
1728  {
1729  interruptSource |= oC_ETH_LLD_InterruptSource_ReceiveOverflowError | oC_ETH_LLD_InterruptSource_ReceiveError;
1730  }
1731 
1732  if(DmaStatus->TransmitUnderflow)
1733  {
1734  interruptSource |= oC_ETH_LLD_InterruptSource_TransmitUnderflowError | oC_ETH_LLD_InterruptSource_TransmitError;
1735  }
1736 
1737  if(DmaStatus->TransmitBufferUnavailable)
1738  {
1739  interruptSource |= oC_ETH_LLD_InterruptSource_TransmitDescriptorError | oC_ETH_LLD_InterruptSource_TransmitError;
1740 
1741  ETH_DMASR->TBUS = 1; /* Clear status */
1742  ETH_DMATPDR->Value = 0xFFFF; /* Resume transmission */
1743  }
1744 
1745  if(DmaStatus->ReceiveBufferUnavailable)
1746  {
1747  interruptSource |= oC_ETH_LLD_InterruptSource_ReceiveDescriptorError | oC_ETH_LLD_InterruptSource_ReceiveError;
1748  }
1749 
1750  if(DmaStatus->FatalBusError)
1751  {
1752  interruptSource |= oC_ETH_LLD_InterruptSource_FatalBusError;
1753  }
1754 
1755  InterruptHandler(interruptSource);
1756 
1757  /* Clearing interrupt status */
1758  ETH_DMASR->Value = 0x1FFFF;
1759  }
1760 }
1761 
1762 #undef _________________________________________INTERRUPTS_SECTION_________________________________________________________________________
1763 
oc_registers.h
The file with interface for registers module.
ClockRange_t
Definition: oc_eth_lld.c:127
oC_InterruptHandler
#define oC_InterruptHandler(BASE_NAME, TYPE_NAME)
Define handler for interrupt.
Definition: oc_interrupts.h:167
oC_Power_On
Something is powered on.
Definition: oc_stdtypes.h:252
Descriptor_t
Definition: oc_eth_lld.c:183
oC_ARRAY_SIZE
#define oC_ARRAY_SIZE(ARRAY)
returns size of static array
Definition: oc_array.h:36
oC_Frequency_t
double oC_Frequency_t
type to store frequency
Definition: oc_frequency.h:76
oc_eth_lld.h
The file with LLD interface for the ETH driver.
oC_Diag_t
Definition: oc_diag.h:25
oC_Diag_SupportedDiagData_t
Definition: oc_diag.h:43
MHz
#define MHz(Freq)
Number of MHz.
Definition: oc_cfg.h:108
oc_lsf.h
The file with interface for LSF module.
oc_mem_lld.h
The file with LLD interface for the MEM driver.
oc_gpio_lld.h
The file with LLD interface for the GPIO driver.
ms
#define ms(time)
Number of ms.
Definition: oc_cfg.h:128
SupportedDiagsArray
static const oC_Diag_SupportedDiagData_t SupportedDiagsArray[]
Definition: oc_eth.c:172
oC_Diag_t::PrintFunction
void(* PrintFunction)(struct oC_Diag_t *Diag)
prints state of the diagnostic
Definition: oc_diag.h:38
oC_MACHINE_MAXIMUM_FREQUENCY
#define oC_MACHINE_MAXIMUM_FREQUENCY
Definition: oc_machine_defs.h:86
oC_MCS_Delay
void oC_MCS_Delay(register oC_UInt_t Cycles)
delays operations for cycles
Definition: oc_mcs.c:679
oc_module.h
The file with interface for the module library.
oC_CLOCK_LLD_GetClockFrequency
oC_Frequency_t oC_CLOCK_LLD_GetClockFrequency(void)
returns frequency of the system clock
Definition: oc_clock_lld.c:237
oC_Module_IsTurnedOn
static bool oC_Module_IsTurnedOn(oC_Module_t Module)
checks if the module is turned on
Definition: oc_module.h:121
oC_Power_Off
Something is powered off.
Definition: oc_stdtypes.h:251
oc_clock_lld.h
The file with LLD interface for the CLOCK driver.
oC_Module_TurnOn
static void oC_Module_TurnOn(oC_Module_t Module)
sets module as turned on
Definition: oc_module.h:170
oc_bits.h
The file with functions for the bits operation.
DmaStatus_t
Definition: oc_eth_lld.c:153
oC_MCS_EnterCriticalSection
static void oC_MCS_EnterCriticalSection(void)
Enters to critical section.
Definition: oc_mcs.h:755
oC_Machine_IsChannelPoweredOn
static bool oC_Machine_IsChannelPoweredOn(oC_Channel_t Channel)
checks if channel is powered on
Definition: oc_machine.h:640
oC_Module_TurnOffVerification
static bool oC_Module_TurnOffVerification(oC_ErrorCode_t *outErrorCode, oC_Module_t Module)
verify if module is turned off
Definition: oc_module.h:155
oC_MCS_ExitCriticalSection
static bool oC_MCS_ExitCriticalSection(void)
Exits from critical section.
Definition: oc_mcs.h:784
oC_Module_TurnOnVerification
static bool oC_Module_TurnOnVerification(oC_ErrorCode_t *outErrorCode, oC_Module_t Module)
verify if module is turned on
Definition: oc_module.h:138
InterruptHandler
static void InterruptHandler(oC_ETH_LLD_InterruptSource_t Source)
handler for interrupts
Definition: oc_eth.c:1124
oC_CLOCK_LLD_DelayForMicroseconds
bool oC_CLOCK_LLD_DelayForMicroseconds(oC_UInt_t Microseconds)
perform a delay for us
Definition: oc_clock_lld.c:297
oC_Machine_SetPowerStateForChannel
static bool oC_Machine_SetPowerStateForChannel(oC_Channel_t Channel, oC_Power_t Power)
configures power state for machine channel
Definition: oc_machine.h:593
oc_channels.h
The file with interface for Channel module.
oc_stdtypes.h
FILE__DESCRIPTION
oC_Channel_EnableInterruptFunction
bool oC_Channel_EnableInterruptFunction(oC_Channel_t Channel, oC_InterruptType_t InterruptType)
enables interrupt according to channel and type
Definition: oc_channels.c:93
NULL
#define NULL
pointer to a zero
Definition: oc_null.h:37
oC_Module_TurnOff
static void oC_Module_TurnOff(oC_Module_t Module)
sets module as turned off
Definition: oc_module.h:185
oc_ba.h
Interface for Machine Base Addresses (BA) module.