Choco OS  V.0.16.9.0
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oc_fmc_lld.c
1 
29 #include <oc_fmc_lld.h>
30 #include <oc_mem_lld.h>
31 #include <oc_bits.h>
32 #include <oc_module.h>
33 #include <oc_lsf.h>
34 #include <oc_stdtypes.h>
35 #include <oc_cfg.h>
36 #include <oc_array.h>
37 #include <oc_gpio_mslld.h>
38 #include <oc_math.h>
39 #include <oc_clock_lld.h>
40 #include <oc_string.h>
41 
47 #define _________________________________________MACROS_SECTION_____________________________________________________________________________
48 
49 #define IsRam(Address) (oC_LSF_IsRamAddress(Address) || oC_LSF_IsExternalAddress(Address))
50 #define IsRom(Address) oC_LSF_IsRomAddress(Address)
51 #define IsExternal(Address) oC_LSF_IsExternalAddress(Address)
52 #define IsAddressCorrect(Address) IsRam(Address) || IsRom(Address)
53 #define IsChannelPoweredOn() (oC_Machine_GetPowerStateForChannel(Channel) == oC_Power_On)
54 #define IsBankUsed(Bank) ((BanksUsage & ((Bank) & Bank_MainBankMask)) != 0)
55 #define GetNumberOfPinsInStructure(PinsType) ( (sizeof(PinsType)) / sizeof(oC_Pin_t) )
56 #define SetBankUsed(Bank) BanksUsage |= (Bank)
57 #define SetBankUnused(Bank) BanksUsage &= ~(Bank)
58 #define FMC_Channel oC_Channel_FMC
59 #define MAX_MEMORY_SIZE oC_MemorySize_MB(512)
60 #define MAX_SDRAM_SIZE oC_MemorySize_MB(512)
61 #define FMC_BCR1 oC_Register(FMC,FMC_BCR1)
62 #define FMC_BCR2 oC_Register(FMC,FMC_BCR2)
63 #define FMC_BCR3 oC_Register(FMC,FMC_BCR3)
64 #define FMC_BCR4 oC_Register(FMC,FMC_BCR4)
65 #define FMC_BTR1 oC_Register(FMC,FMC_BTR1)
66 #define FMC_BTR2 oC_Register(FMC,FMC_BTR2)
67 #define FMC_BTR3 oC_Register(FMC,FMC_BTR3)
68 #define FMC_BTR4 oC_Register(FMC,FMC_BTR4)
69 #define FMC_BWTR1 oC_Register(FMC,FMC_BWTR1)
70 #define FMC_BWTR2 oC_Register(FMC,FMC_BWTR2)
71 #define FMC_BWTR3 oC_Register(FMC,FMC_BWTR3)
72 #define FMC_BWTR4 oC_Register(FMC,FMC_BWTR4)
73 #define FMC_PCR oC_Register(FMC,FMC_PCR)
74 #define FMC_SR oC_Register(FMC,FMC_SR)
75 #define FMC_PMEM oC_Register(FMC,FMC_PMEM)
76 #define FMC_PATT oC_Register(FMC,FMC_PATT)
77 #define FMC_ECCR oC_Register(FMC,FMC_ECCR)
78 #define FMC_SDCR1 oC_Register(FMC,FMC_SDCR1)
79 #define FMC_SDCR2 oC_Register(FMC,FMC_SDCR2)
80 #define FMC_SDTR1 oC_Register(FMC,FMC_SDTR1)
81 #define FMC_SDTR2 oC_Register(FMC,FMC_SDTR2)
82 #define FMC_SDCMR oC_Register(FMC,FMC_SDCMR)
83 #define FMC_SDRTR oC_Register(FMC,FMC_SDRTR)
84 #define FMC_SDSR oC_Register(FMC,FMC_SDSR)
85 #define SDRC1_BIT_MASK 0x7C00
86 #define SDRC2_BIT_MASK 0x3FF
87 #define SDTR1_BIT_MASK 0xF0F000
88 #define SDTR2_BIT_MASK 0xF0F0FFF
89 
90 #undef _________________________________________MACROS_SECTION_____________________________________________________________________________
91 
97 #define _________________________________________TYPES_SECTION______________________________________________________________________________
98 
99 //==========================================================================================================================================
103 //==========================================================================================================================================
104 typedef enum
105 {
106  Bank_SubBankMask = 0xF ,
107  Bank_SubBank1 = (1<<0) ,
108  Bank_SubBank2 = (1<<1) ,
109  Bank_SubBank3 = (1<<2) ,
110  Bank_SubBank4 = (1<<3) ,
111  Bank_MainBankMask = 0xF0 ,
112  Bank_MainBank1 = (1<<4) ,
113  Bank_MainBank3 = (1<<5) ,
114  Bank_MainBank5 = (1<<6) ,
115  Bank_MainBank6 = (1<<7) ,
116  Bank_1_NOR_PSRAM1 = Bank_MainBank1 | Bank_SubBank1 ,
117  Bank_1_NOR_PSRAM2 = Bank_MainBank1 | Bank_SubBank2 ,
118  Bank_1_NOR_PSRAM3 = Bank_MainBank1 | Bank_SubBank3 ,
119  Bank_1_NOR_PSRAM4 = Bank_MainBank1 | Bank_SubBank4 ,
120  Bank_3_NAND_FlashMemory1 = Bank_MainBank3 | Bank_SubBank1 ,
121  Bank_3_NAND_FlashMemory2 = Bank_MainBank3 | Bank_SubBank2 ,
122  Bank_3_NAND_FlashMemory3 = Bank_MainBank3 | Bank_SubBank3 ,
123  Bank_3_NAND_FlashMemory4 = Bank_MainBank3 | Bank_SubBank4 ,
124  Bank_5_SDRAM1 = Bank_MainBank5 | Bank_SubBank1 ,
125  Bank_5_SDRAM2 = Bank_MainBank5 | Bank_SubBank2 ,
126  Bank_5_SDRAM3 = Bank_MainBank5 | Bank_SubBank3 ,
127  Bank_5_SDRAM4 = Bank_MainBank5 | Bank_SubBank4 ,
128  Bank_6_SDRAM1 = Bank_MainBank6 | Bank_SubBank1 ,
129  Bank_6_SDRAM2 = Bank_MainBank6 | Bank_SubBank2 ,
130  Bank_6_SDRAM3 = Bank_MainBank6 | Bank_SubBank3 ,
131  Bank_6_SDRAM4 = Bank_MainBank6 | Bank_SubBank4 ,
132 } Bank_t;
133 
134 //==========================================================================================================================================
138 //==========================================================================================================================================
139 typedef struct
140 {
141  void * StartAddress;
142  void * EndAddress;
143  oC_UInt_t Size;
144  Bank_t Bank;
145  oC_FMC_LLD_MemoryType_t MemoryType;
146 } BankData_t;
147 
148 //==========================================================================================================================================
152 //==========================================================================================================================================
153 typedef enum
154 {
155  CommandMode_NormalMode ,
156  CommandMode_ClockConfigurationEnable ,
157  CommandMode_AllBankPrecharge ,
158  CommandMode_AutoRefresh ,
159  CommandMode_LoadModeRegister ,
160  CommandMode_SelfRefresh ,
161  CommandMode_PowerDown
162 } CommandMode_t;
163 
164 //==========================================================================================================================================
168 //==========================================================================================================================================
169 typedef struct
170 {
171  CommandMode_t CommandMode;
172  uint32_t AutoRefreshNumber;
173  uint32_t ModeRegisterDefinition;
174 } SDRAMCommand_t;
175 
176 //==========================================================================================================================================
180 //==========================================================================================================================================
181 typedef struct
182 {
183  oC_RegisterType_FMC_SDCR1_t SDCR;
184  oC_RegisterType_FMC_SDTR1_t SDTR;
185 } SDRAMConfigVariables_t;
186 
187 #undef _________________________________________TYPES_SECTION______________________________________________________________________________
188 
189 
195 #define _________________________________________VARIABLES_SECTION__________________________________________________________________________
196 
197 static Bank_t BanksUsage = 0;
198 static const BankData_t BankDatas[] = {
199  /* =========================== BANK 1 ============================== */
200  {
201  .Bank = Bank_1_NOR_PSRAM1 ,
202  .MemoryType = oC_FMC_LLD_MemoryType_NOR_Flash | oC_FMC_LLD_MemoryType_PSRAM ,
203  .StartAddress = (void*)0x60000000 ,
204  .EndAddress = (void*)0x64000000 ,
205  .Size = MB(64)
206  } ,
207  {
208  .Bank = Bank_1_NOR_PSRAM2 ,
209  .MemoryType = oC_FMC_LLD_MemoryType_NOR_Flash | oC_FMC_LLD_MemoryType_PSRAM ,
210  .StartAddress = (void*)0x64000000 ,
211  .EndAddress = (void*)0x68000000 ,
212  .Size = MB(64)
213  } ,
214  {
215  .Bank = Bank_1_NOR_PSRAM3 ,
216  .MemoryType = oC_FMC_LLD_MemoryType_NOR_Flash | oC_FMC_LLD_MemoryType_PSRAM ,
217  .StartAddress = (void*)0x68000000 ,
218  .EndAddress = (void*)0x6C000000 ,
219  .Size = MB(64)
220  } ,
221  {
222  .Bank = Bank_1_NOR_PSRAM4 ,
223  .MemoryType = oC_FMC_LLD_MemoryType_NOR_Flash | oC_FMC_LLD_MemoryType_PSRAM ,
224  .StartAddress = (void*)0x6C000000 ,
225  .EndAddress = (void*)0x70000000 ,
226  .Size = MB(64)
227  } ,
228  /* =========================== BANK 3 ============================== */
229  {
230  .Bank = Bank_3_NAND_FlashMemory1 ,
231  .MemoryType = oC_FMC_LLD_MemoryType_NAND_Flash ,
232  .StartAddress = (void*)0x80000000 ,
233  .EndAddress = (void*)0x84000000 ,
234  .Size = MB(64)
235  } ,
236  {
237  .Bank = Bank_3_NAND_FlashMemory2 ,
238  .MemoryType = oC_FMC_LLD_MemoryType_NAND_Flash ,
239  .StartAddress = (void*)0x84000000 ,
240  .EndAddress = (void*)0x88000000 ,
241  .Size = MB(64)
242  } ,
243  {
244  .Bank = Bank_3_NAND_FlashMemory3 ,
245  .MemoryType = oC_FMC_LLD_MemoryType_NAND_Flash ,
246  .StartAddress = (void*)0x88000000 ,
247  .EndAddress = (void*)0x8C000000 ,
248  .Size = MB(64)
249  } ,
250  {
251  .Bank = Bank_3_NAND_FlashMemory4 ,
252  .MemoryType = oC_FMC_LLD_MemoryType_NAND_Flash ,
253  .StartAddress = (void*)0x8C000000 ,
254  .EndAddress = (void*)0x90000000 ,
255  .Size = MB(64)
256  } ,
257  /* =========================== BANK 5 ============================== */
258  {
259  .Bank = Bank_5_SDRAM1 ,
260  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
261  .StartAddress = (void*)0xC0000000 ,
262  .EndAddress = (void*)0xC4000000 ,
263  .Size = MB(64)
264  } ,
265  {
266  .Bank = Bank_5_SDRAM2 ,
267  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
268  .StartAddress = (void*)0xC4000000 ,
269  .EndAddress = (void*)0xC8000000 ,
270  .Size = MB(64)
271  } ,
272  {
273  .Bank = Bank_5_SDRAM3 ,
274  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
275  .StartAddress = (void*)0xC8000000 ,
276  .EndAddress = (void*)0xCC000000 ,
277  .Size = MB(64)
278  } ,
279  {
280  .Bank = Bank_5_SDRAM4 ,
281  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
282  .StartAddress = (void*)0xCC000000 ,
283  .EndAddress = (void*)0xD0000000 ,
284  .Size = MB(64)
285  } ,
286  /* =========================== BANK 6 ============================== */
287  {
288  .Bank = Bank_6_SDRAM1 ,
289  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
290  .StartAddress = (void*)0xD0000000 ,
291  .EndAddress = (void*)0xD4000000 ,
292  .Size = MB(64)
293  } ,
294  {
295  .Bank = Bank_6_SDRAM2 ,
296  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
297  .StartAddress = (void*)0xD4000000 ,
298  .EndAddress = (void*)0xD8000000 ,
299  .Size = MB(64)
300  } ,
301  {
302  .Bank = Bank_6_SDRAM3 ,
303  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
304  .StartAddress = (void*)0xD8000000 ,
305  .EndAddress = (void*)0xDC000000 ,
306  .Size = MB(64)
307  } ,
308  {
309  .Bank = Bank_6_SDRAM4 ,
310  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
311  .StartAddress = (void*)0xDC000000 ,
312  .EndAddress = (void*)0xE0000000 ,
313  .Size = MB(64)
314  } ,
315 };
316 
317 
318 #undef _________________________________________VARIABLES_SECTION__________________________________________________________________________
319 
325 #define _________________________________________LOCAL_PROTOTYPES_SECTION___________________________________________________________________
326 
327 static inline bool IsProtectionCorrect ( oC_FMC_LLD_Protection_t Protection );
328 static inline bool IsDataBusWidthCorrect ( oC_FMC_LLD_DataBusWidth_t DataBusWidth );
329 static inline bool IsDataBusWidthSupported ( oC_FMC_LLD_DataBusWidth_t DataBusWidth );
330 static oC_ErrorCode_t ConnectSDRAMModulePins ( const oC_FMC_LLD_SDRAM_Pins_t * Pins , oC_FMC_LLD_Result_t * Result );
331 static oC_ErrorCode_t DisconnectModulePins ( const oC_Pin_t * Pins , oC_FMC_LLD_PinUsage_t * PinsUsage , oC_UInt_t NumberOfPins );
332 static bool FindFreeBanks ( oC_FMC_LLD_MemoryType_t MemoryType , oC_MemorySize_t MemorySize , const oC_FMC_LLD_SDRAM_Pins_t * Pins, Bank_t * outBanks , uint8_t ** outAddress );
333 static oC_ErrorCode_t ConfigureSDRAM ( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , SDRAMConfigVariables_t * outVariables , oC_FMC_LLD_Result_t * outResult );
334 static oC_ErrorCode_t UnconfigureSDRAM ( const oC_FMC_LLD_SDRAM_Config_t * Config );
335 static oC_ErrorCode_t ConnectModulePin ( oC_Pin_t Pin , oC_PinFunction_t PinFunction , oC_FMC_LLD_PinUsage_t * PinUsage);
336 static oC_ErrorCode_t DisconnectPin ( oC_Pin_t Pin );
337 static uint32_t TimeToCycles ( oC_Time_t Time , oC_Frequency_t Frequency );
338 static bool SetTimeInCycles ( uint32_t * outCycles , oC_Time_t Time , oC_Frequency_t Frequency , uint32_t Min , uint32_t Max , uint32_t Default );
339 static bool SendSDRAMCommand ( oC_Time_t * Timeout , SDRAMCommand_t * Command , Bank_t Banks );
340 static oC_ErrorCode_t CountSDRAMConfigVariables ( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , SDRAMConfigVariables_t * outVariables , oC_FMC_LLD_Result_t * outResult );
341 static void CountSDRAMRequiredPins ( const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult );
342 
343 #undef _________________________________________LOCAL_PROTOTYPES_SECTION___________________________________________________________________
344 
345 
351 #define _________________________________________FUNCTIONS_SECTION__________________________________________________________________________
352 
353 //==========================================================================================================================================
358 //==========================================================================================================================================
359 oC_ErrorCode_t oC_FMC_LLD_TurnOnDriver( void )
360 {
361  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
362 
363  oC_MCS_EnterCriticalSection();
364 
365  if(oC_Module_TurnOffVerification(&errorCode , oC_Module_FMC_LLD))
366  {
367  oC_Module_TurnOn(oC_Module_FMC_LLD);
368  BanksUsage = 0;
369  errorCode = oC_ErrorCode_None;
370  }
371 
372  oC_MCS_ExitCriticalSection();
373 
374  return errorCode;
375 }
376 
377 //==========================================================================================================================================
382 //==========================================================================================================================================
383 oC_ErrorCode_t oC_FMC_LLD_TurnOffDriver( void )
384 {
385  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
386 
387  oC_MCS_EnterCriticalSection();
388 
389  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_FMC_LLD))
390  {
391  oC_Module_TurnOff(oC_Module_FMC_LLD);
392  errorCode = oC_ErrorCode_None;
393  }
394 
395  oC_MCS_ExitCriticalSection();
396 
397  return errorCode;
398 }
399 
400 //==========================================================================================================================================
405 //==========================================================================================================================================
406 oC_ErrorCode_t oC_FMC_LLD_ConfigureSDRAM( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
407 {
408  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
409  SDRAMConfigVariables_t configVariables;
410 
411  memset(&configVariables,0,sizeof(configVariables));
412 
413  if(oC_Module_TurnOnVerification(&errorCode,oC_Module_FMC_LLD))
414  {
415  oC_MCS_EnterCriticalSection();
416 
417  if(
418  ErrorCondition( IsAddressCorrect(Config) , oC_ErrorCode_WrongConfigAddress )
419  && ErrorCondition( IsAddressCorrect(ChipInfo) , oC_ErrorCode_WrongAddress )
420  && ErrorCondition( IsRam(outResult) , oC_ErrorCode_OutputAddressNotInRAM )
421  && ErrorCondition( ChipInfo->MemoryType == oC_FMC_LLD_MemoryType_SDRAM , oC_ErrorCode_MemoryTypeNotCorrect )
422  )
423  {
424  if(
425  oC_AssignErrorCode(&errorCode , CountSDRAMConfigVariables( Config , ChipInfo, &configVariables , outResult ))
426  && oC_AssignErrorCode(&errorCode , ConnectSDRAMModulePins ( &Config->Pins , outResult ))
427  && oC_AssignErrorCode(&errorCode , ConfigureSDRAM ( Config , ChipInfo, &configVariables , outResult ))
428  )
429  {
430  SetBankUsed(outResult->ConfiguredBanks);
431  errorCode = oC_ErrorCode_None;
432  }
433  else
434  {
435  memset(outResult,0,sizeof(oC_FMC_LLD_Result_t));
436  }
437  }
438 
439  oC_MCS_ExitCriticalSection();
440  }
441 
442  return errorCode;
443 }
444 
445 //==========================================================================================================================================
450 //==========================================================================================================================================
451 oC_ErrorCode_t oC_FMC_LLD_ConfigureNORFlash( const oC_FMC_LLD_NORFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
452 {
453  return oC_ErrorCode_NotImplemented;
454 }
455 
456 //==========================================================================================================================================
461 //==========================================================================================================================================
462 oC_ErrorCode_t oC_FMC_LLD_ConfigureNANDFlash(const oC_FMC_LLD_NANDFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
463 {
464  return oC_ErrorCode_NotImplemented;
465 }
466 
467 //==========================================================================================================================================
472 //==========================================================================================================================================
473 oC_ErrorCode_t oC_FMC_LLD_ConfigurePSRAM( const oC_FMC_LLD_PSRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
474 {
475  return oC_ErrorCode_NotImplemented;
476 }
477 
478 //==========================================================================================================================================
483 //==========================================================================================================================================
484 oC_ErrorCode_t oC_FMC_LLD_UnconfigureSDRAM( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
485 {
486  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
487 
488  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_FMC_LLD))
489  {
490  if(
491  ErrorCondition( IsRam(Config) || IsRom(Config) , oC_ErrorCode_WrongConfigAddress ) &&
492  ErrorCondition( IsRam(outResult) , oC_ErrorCode_OutputAddressNotInRAM )
493  )
494  {
495  oC_MCS_EnterCriticalSection();
496 
497  if(
498  oC_AssignErrorCode(&errorCode , DisconnectModulePins(Config->Pins.PinsArray,outResult->PinsUsage,GetNumberOfPinsInStructure(oC_FMC_LLD_SDRAM_Pins_t)) ) &&
499  oC_AssignErrorCode(&errorCode , UnconfigureSDRAM(Config) )
500  )
501  {
502  SetBankUnused(outResult->ConfiguredBanks);
503  errorCode = oC_ErrorCode_None;
504  }
505 
506  oC_MCS_ExitCriticalSection();
507  }
508  }
509 
510  return errorCode;
511 }
512 
513 //==========================================================================================================================================
518 //==========================================================================================================================================
519 oC_ErrorCode_t oC_FMC_LLD_UnconfigureNORFlash( const oC_FMC_LLD_NORFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
520 {
521  return oC_ErrorCode_NotImplemented;
522 }
523 
524 //==========================================================================================================================================
529 //==========================================================================================================================================
530 oC_ErrorCode_t oC_FMC_LLD_UnconfigureNANDFlash(const oC_FMC_LLD_NANDFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
531 {
532  return oC_ErrorCode_NotImplemented;
533 }
534 
535 //==========================================================================================================================================
540 //==========================================================================================================================================
541 oC_ErrorCode_t oC_FMC_LLD_UnconfigurePSRAM( const oC_FMC_LLD_PSRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
542 {
543  return oC_ErrorCode_NotImplemented;
544 }
545 
546 //==========================================================================================================================================
551 //==========================================================================================================================================
552 oC_ErrorCode_t oC_FMC_LLD_SendSDRAMCommand( oC_FMC_LLD_Result_t * Result , oC_Time_t * Timeout , oC_FMC_LLD_SDRAM_Command_t Command , const oC_FMC_LLD_SDRAM_CommandData_t * Data )
553 {
554  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
555 
556  if(
557  oC_Module_TurnOnVerification(&errorCode , oC_Module_FMC_LLD ) &&
558  ErrorCondition( IsRam(Result) , oC_ErrorCode_WrongAddress )
559  )
560  {
561  bool sendCommand = false;
562  SDRAMCommand_t command = {0};
563 
564  switch(Command)
565  {
566  case oC_FMC_LLD_SDRAM_Command_EnableClock:
567  command.CommandMode = CommandMode_ClockConfigurationEnable;
568  command.AutoRefreshNumber = 1;
569  command.ModeRegisterDefinition = 0;
570  sendCommand = true;
571  errorCode = oC_ErrorCode_None;
572  break;
573  case oC_FMC_LLD_SDRAM_Command_Inhibit :
574  sendCommand = false;
575  errorCode = oC_ErrorCode_None;
576  break;
577  case oC_FMC_LLD_SDRAM_Command_Nop :
578  sendCommand = false;
579  errorCode = oC_ErrorCode_None;
580  break;
581  case oC_FMC_LLD_SDRAM_Command_LoadModeRegister:
582  if(ErrorCondition(IsRam(Data) || IsRom(Data) , oC_ErrorCode_WrongAddress))
583  {
584  command.CommandMode = CommandMode_LoadModeRegister;
585  command.AutoRefreshNumber = 1;
586  command.ModeRegisterDefinition = Data->LoadModeRegister.MRD;
587  sendCommand = true;
588  errorCode = oC_ErrorCode_None;
589  }
590  break;
591  case oC_FMC_LLD_SDRAM_Command_Active:
592  errorCode = oC_ErrorCode_NotImplemented;
593  break;
594  case oC_FMC_LLD_SDRAM_Command_Read:
595  errorCode = oC_ErrorCode_NotImplemented;
596  break;
597  case oC_FMC_LLD_SDRAM_Command_Write:
598  errorCode = oC_ErrorCode_NotImplemented;
599  break;
600  case oC_FMC_LLD_SDRAM_Command_Precharge:
601  if(ErrorCondition(IsRam(Data) || IsRom(Data) , oC_ErrorCode_WrongAddress))
602  {
603  command.CommandMode = CommandMode_AllBankPrecharge;
604  command.AutoRefreshNumber = 1;
605  command.ModeRegisterDefinition = 0;
606  sendCommand = true;
607  errorCode = oC_ErrorCode_None;
608  }
609  break;
610  case oC_FMC_LLD_SDRAM_Command_BurstTerminate:
611  errorCode = oC_ErrorCode_NotImplemented;
612  break;
613  case oC_FMC_LLD_SDRAM_Command_AutoRefresh:
614  if(ErrorCondition(IsRam(Data) || IsRom(Data) , oC_ErrorCode_WrongAddress))
615  {
616  command.CommandMode = CommandMode_AutoRefresh;
617  command.AutoRefreshNumber = Data->AutoRefresh.NumberOfAutoRefresh;
618  command.ModeRegisterDefinition = 0;
619  sendCommand = true;
620  errorCode = oC_ErrorCode_None;
621  }
622  break;
623  case oC_FMC_LLD_SDRAM_Command_SelfRefresh:
624  if(ErrorCondition(IsRam(Data) || IsRom(Data) , oC_ErrorCode_WrongAddress))
625  {
626  command.CommandMode = CommandMode_SelfRefresh;
627  command.AutoRefreshNumber = Data->AutoRefresh.NumberOfAutoRefresh;
628  command.ModeRegisterDefinition = 0;
629  sendCommand = true;
630  errorCode = oC_ErrorCode_None;
631  }
632  break;
633  default:
634  errorCode = oC_ErrorCode_CommandNotCorrect;
635  break;
636  }
637 
638  if(!oC_ErrorOccur(errorCode) && sendCommand == true)
639  {
640  if(ErrorCondition(SendSDRAMCommand(Timeout,&command,Result->ConfiguredBanks) , oC_ErrorCode_Timeout))
641  {
642  errorCode = oC_ErrorCode_None;
643  }
644  }
645  }
646 
647  return errorCode;
648 }
649 
650 //==========================================================================================================================================
655 //==========================================================================================================================================
656 oC_ErrorCode_t oC_FMC_LLD_FinishSDRAMInitialization( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * Result )
657 {
658  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
659 
660  if(oC_Module_TurnOnVerification(&errorCode,oC_Module_FMC_LLD))
661  {
662  if(
663  ErrorCondition( IsAddressCorrect(Config) , oC_ErrorCode_WrongConfigAddress )
664  && ErrorCondition( IsAddressCorrect(ChipInfo) , oC_ErrorCode_WrongAddress )
665  && ErrorCondition( IsRam(Result) , oC_ErrorCode_OutputAddressNotInRAM )
666  && ErrorCondition( IsExternal(Result->MemoryStart) , oC_ErrorCode_MemoryNotConfigured )
667  && ErrorCondition( Result->DataBusWidth > 0 && Result->DataBusWidth <= 4 , oC_ErrorCode_MemoryNotConfigured )
668  && ErrorCondition( Result->ConfiguredFrequency > 0 , oC_ErrorCode_MemoryNotConfigured )
669  && ErrorCondition( ChipInfo->MemoryType == oC_FMC_LLD_MemoryType_SDRAM , oC_ErrorCode_MemoryTypeNotCorrect )
670  && ErrorCondition( ChipInfo->SDRAM.NumberOfRowAddressBits >= 11 , oC_ErrorCode_RowBitsNumberNotSupported )
671  && ErrorCondition( ChipInfo->SDRAM.NumberOfRowAddressBits <= 13 , oC_ErrorCode_RowBitsNumberNotSupported )
672  && ErrorCondition( ChipInfo->SDRAM.AutoRefreshPeriod > 0 , oC_ErrorCode_AutoRefreshPeriodNotCorrect)
673  && ErrorCondition( ChipInfo->SDRAM.MaximumClockFrequency > 0 , oC_ErrorCode_WrongFrequency )
674  )
675  {
676  /* Counting maximum number of rows, that is possible for the chip */
677  uint32_t maximumNumberOfRows = oC_Bits_Mask_U32(0,ChipInfo->SDRAM.NumberOfRowAddressBits);
678 
679  /* Counting number of used rows according to the configured data bus width */
680  maximumNumberOfRows /= ChipInfo->SDRAM.DataBusWidth / Result->DataBusWidth;
681 
682  /* Counting refresh rate in number of SDCLK clock cycles between the refresh cycles */
683  uint32_t count = (uint32_t)((ChipInfo->SDRAM.AutoRefreshPeriod / ((double)maximumNumberOfRows)) * Result->ConfiguredFrequency);
684 
685  if(count <= oC_Bits_Mask_U32(0,12))
686  {
687  FMC_SDRTR->COUNT = count;
688  errorCode = oC_ErrorCode_None;
689  }
690  else
691  {
692  errorCode = oC_ErrorCode_FrequencyNotPossible;
693  }
694  }
695  }
696 
697  return errorCode;
698 }
699 
700 //==========================================================================================================================================
705 //==========================================================================================================================================
706 oC_ErrorCode_t oC_FMC_LLD_FinishNORFlashInitialization( const oC_FMC_LLD_NORFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * Result )
707 {
708  return oC_ErrorCode_NotImplemented;
709 }
710 
711 //==========================================================================================================================================
716 //==========================================================================================================================================
717 oC_ErrorCode_t oC_FMC_LLD_FinishNANDFlashInitialization( const oC_FMC_LLD_NANDFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * Result )
718 {
719  return oC_ErrorCode_NotImplemented;
720 }
721 
722 //==========================================================================================================================================
727 //==========================================================================================================================================
728 oC_ErrorCode_t oC_FMC_LLD_FinishPSRAMInitialization( const oC_FMC_LLD_PSRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * Result )
729 {
730  return oC_ErrorCode_NotImplemented;
731 }
732 
733 #undef _________________________________________FUNCTIONS_SECTION__________________________________________________________________________
734 
740 #define _________________________________________LOCAL_FUNCTIONS_SECTION____________________________________________________________________
741 
742 //==========================================================================================================================================
746 //==========================================================================================================================================
747 static inline bool IsProtectionCorrect( oC_FMC_LLD_Protection_t Protection )
748 {
749  return Protection == 0 ||
750  Protection <= (oC_FMC_LLD_Protection_AllowExecute | oC_FMC_LLD_Protection_AllowRead | oC_FMC_LLD_Protection_AllowWrite);
751 }
752 
753 //==========================================================================================================================================
757 //==========================================================================================================================================
758 static inline bool IsDataBusWidthCorrect( oC_FMC_LLD_DataBusWidth_t DataBusWidth )
759 {
760  oC_STATIC_ASSERT(oC_FMC_LLD_DataBusWidth_8Bits == 1 , "data bus width must be equal to the number of used bytes!");
761  oC_STATIC_ASSERT(oC_FMC_LLD_DataBusWidth_16Bits == 2 , "data bus width must be equal to the number of used bytes!");
762  oC_STATIC_ASSERT(oC_FMC_LLD_DataBusWidth_32Bits == 4 , "data bus width must be equal to the number of used bytes!");
763  oC_STATIC_ASSERT(oC_FMC_LLD_DataBusWidth_64Bits == 8 , "data bus width must be equal to the number of used bytes!");
764 
765  return DataBusWidth == oC_FMC_LLD_DataBusWidth_8Bits
766  || DataBusWidth == oC_FMC_LLD_DataBusWidth_16Bits
767  || DataBusWidth == oC_FMC_LLD_DataBusWidth_32Bits
768  || DataBusWidth == oC_FMC_LLD_DataBusWidth_64Bits;
769 }
770 
771 //==========================================================================================================================================
775 //==========================================================================================================================================
776 static inline bool IsDataBusWidthSupported( oC_FMC_LLD_DataBusWidth_t DataBusWidth )
777 {
778  return DataBusWidth == oC_FMC_LLD_DataBusWidth_8Bits
779  || DataBusWidth == oC_FMC_LLD_DataBusWidth_16Bits
780  || DataBusWidth == oC_FMC_LLD_DataBusWidth_32Bits;
781 }
782 
783 
784 //==========================================================================================================================================
788 //==========================================================================================================================================
789 static oC_ErrorCode_t ConnectSDRAMModulePins( const oC_FMC_LLD_SDRAM_Pins_t * Pins , oC_FMC_LLD_Result_t * Result )
790 {
791  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
792 
793  oC_Procedure_Begin
794  {
795  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDCLK , oC_FMC_PinFunction_FMC_SDCLK , &Result->SDCLK ) );
796 
797  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDCKE[0] , oC_FMC_PinFunction_FMC_SDCKE0 , &Result->SDCKE[0] ) );
798  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDCKE[1] , oC_FMC_PinFunction_FMC_SDCKE1 , &Result->SDCKE[1] ) );
799 
800 
801  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDNE[0] , oC_FMC_PinFunction_FMC_SDNE0 , &Result->SDNE[0] ) );
802  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDNE[1] , oC_FMC_PinFunction_FMC_SDNE1 , &Result->SDNE[1] ) );
803 
804 
805  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 0] , oC_FMC_PinFunction_FMC_A0 , &Result->A[ 0] ) );
806  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 1] , oC_FMC_PinFunction_FMC_A1 , &Result->A[ 1] ) );
807  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 2] , oC_FMC_PinFunction_FMC_A2 , &Result->A[ 2] ) );
808  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 3] , oC_FMC_PinFunction_FMC_A3 , &Result->A[ 3] ) );
809  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 4] , oC_FMC_PinFunction_FMC_A4 , &Result->A[ 4] ) );
810  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 5] , oC_FMC_PinFunction_FMC_A5 , &Result->A[ 5] ) );
811  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 6] , oC_FMC_PinFunction_FMC_A6 , &Result->A[ 6] ) );
812  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 7] , oC_FMC_PinFunction_FMC_A7 , &Result->A[ 7] ) );
813  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 8] , oC_FMC_PinFunction_FMC_A8 , &Result->A[ 8] ) );
814  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 9] , oC_FMC_PinFunction_FMC_A9 , &Result->A[ 9] ) );
815  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[10] , oC_FMC_PinFunction_FMC_A10 , &Result->A[10] ) );
816  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[11] , oC_FMC_PinFunction_FMC_A11 , &Result->A[11] ) );
817  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[12] , oC_FMC_PinFunction_FMC_A12 , &Result->A[12] ) );
818 
819 
820  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 0] , oC_FMC_PinFunction_FMC_D0 , &Result->D[ 0] ) );
821  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 1] , oC_FMC_PinFunction_FMC_D1 , &Result->D[ 1] ) );
822  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 2] , oC_FMC_PinFunction_FMC_D2 , &Result->D[ 2] ) );
823  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 3] , oC_FMC_PinFunction_FMC_D3 , &Result->D[ 3] ) );
824  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 4] , oC_FMC_PinFunction_FMC_D4 , &Result->D[ 4] ) );
825  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 5] , oC_FMC_PinFunction_FMC_D5 , &Result->D[ 5] ) );
826  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 6] , oC_FMC_PinFunction_FMC_D6 , &Result->D[ 6] ) );
827  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 7] , oC_FMC_PinFunction_FMC_D7 , &Result->D[ 7] ) );
828  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 8] , oC_FMC_PinFunction_FMC_D8 , &Result->D[ 8] ) );
829  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 9] , oC_FMC_PinFunction_FMC_D9 , &Result->D[ 9] ) );
830  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[10] , oC_FMC_PinFunction_FMC_D10 , &Result->D[10] ) );
831  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[11] , oC_FMC_PinFunction_FMC_D11 , &Result->D[11] ) );
832  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[12] , oC_FMC_PinFunction_FMC_D12 , &Result->D[12] ) );
833  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[13] , oC_FMC_PinFunction_FMC_D13 , &Result->D[13] ) );
834  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[14] , oC_FMC_PinFunction_FMC_D14 , &Result->D[14] ) );
835  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[15] , oC_FMC_PinFunction_FMC_D15 , &Result->D[15] ) );
836  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[16] , oC_FMC_PinFunction_FMC_D16 , &Result->D[16] ) );
837  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[17] , oC_FMC_PinFunction_FMC_D17 , &Result->D[17] ) );
838  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[18] , oC_FMC_PinFunction_FMC_D18 , &Result->D[18] ) );
839  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[19] , oC_FMC_PinFunction_FMC_D19 , &Result->D[19] ) );
840  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[20] , oC_FMC_PinFunction_FMC_D20 , &Result->D[20] ) );
841  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[21] , oC_FMC_PinFunction_FMC_D21 , &Result->D[21] ) );
842  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[22] , oC_FMC_PinFunction_FMC_D22 , &Result->D[22] ) );
843  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[23] , oC_FMC_PinFunction_FMC_D23 , &Result->D[23] ) );
844  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[24] , oC_FMC_PinFunction_FMC_D24 , &Result->D[24] ) );
845  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[25] , oC_FMC_PinFunction_FMC_D25 , &Result->D[25] ) );
846  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[26] , oC_FMC_PinFunction_FMC_D26 , &Result->D[26] ) );
847  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[27] , oC_FMC_PinFunction_FMC_D27 , &Result->D[27] ) );
848  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[28] , oC_FMC_PinFunction_FMC_D28 , &Result->D[28] ) );
849  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[29] , oC_FMC_PinFunction_FMC_D29 , &Result->D[29] ) );
850  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[30] , oC_FMC_PinFunction_FMC_D30 , &Result->D[30] ) );
851  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[31] , oC_FMC_PinFunction_FMC_D31 , &Result->D[31] ) );
852 
853  oC_Procedure_ExitIfError(ConnectModulePin( Pins->BA[0] , oC_FMC_PinFunction_FMC_BA0 , &Result->BA[0] ) );
854  oC_Procedure_ExitIfError(ConnectModulePin( Pins->BA[1] , oC_FMC_PinFunction_FMC_BA1 , &Result->BA[1] ) );
855 
856  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NRAS , oC_FMC_PinFunction_FMC_SDNRAS , &Result->NRAS ) );
857  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NCAS , oC_FMC_PinFunction_FMC_SDNCAS , &Result->NCAS ) );
858  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDNWE , oC_FMC_PinFunction_FMC_SDNWE , &Result->SDNWE ) );
859 
860  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NBL[0] , oC_FMC_PinFunction_FMC_NBL0 , &Result->NBL[0] ) );
861  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NBL[1] , oC_FMC_PinFunction_FMC_NBL1 , &Result->NBL[1] ) );
862  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NBL[2] , oC_FMC_PinFunction_FMC_NBL2 , &Result->NBL[2] ) );
863  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NBL[3] , oC_FMC_PinFunction_FMC_NBL3 , &Result->NBL[3] ) );
864 
865  errorCode = oC_ErrorCode_None;
866  }
867  oC_Procedure_End;
868 
869  if(oC_ErrorOccur(errorCode))
870  {
871  DisconnectModulePins(Pins->PinsArray,Result->PinsUsage,GetNumberOfPinsInStructure(oC_FMC_LLD_SDRAM_Pins_t));
872  }
873 
874  return errorCode;
875 }
876 
877 //==========================================================================================================================================
881 //==========================================================================================================================================
882 static oC_ErrorCode_t DisconnectModulePins( const oC_Pin_t * Pins , oC_FMC_LLD_PinUsage_t * PinsUsage , oC_UInt_t NumberOfPins )
883 {
884  oC_ErrorCode_t errorCode = oC_ErrorCode_None;
885 
886  for(uint32_t pinIndex = 0; pinIndex < NumberOfPins ; pinIndex++)
887  {
888  if(PinsUsage[pinIndex] == oC_FMC_LLD_PinUsage_Used)
889  {
890  oC_AssignErrorCode(&errorCode,DisconnectPin(Pins[pinIndex]));
891  }
892  }
893 
894  return errorCode;
895 }
896 
897 //==========================================================================================================================================
901 //==========================================================================================================================================
902 static bool FindFreeBanks( oC_FMC_LLD_MemoryType_t MemoryType , oC_MemorySize_t MemorySize , const oC_FMC_LLD_SDRAM_Pins_t * Pins, Bank_t * outBanks , uint8_t ** outAddress )
903 {
904  Bank_t banks = 0;
905  BankData_t foundBankData = {0};
906  uint8_t numberOfSDRAMbank = 1;
907 
908  oC_ARRAY_FOREACH_IN_ARRAY(BankDatas,bankData)
909  {
910  if(IsBankUsed(bankData->Bank) == false)
911  {
912  if(bankData->MemoryType == MemoryType && bankData->MemoryType != oC_FMC_LLD_MemoryType_SDRAM)
913  {
914  /* If this is the first bank that has been found */
915  if(foundBankData.Bank == 0)
916  {
917  foundBankData.Bank = bankData->Bank;
918  foundBankData.StartAddress = bankData->StartAddress;
919  foundBankData.EndAddress = bankData->EndAddress;
920  foundBankData.MemoryType = bankData->MemoryType;
921  foundBankData.Size = bankData->Size;
922  }
923  /* If some bank was found before */
924  else
925  {
926  if(bankData->StartAddress == foundBankData.EndAddress)
927  {
928  foundBankData.Bank |= bankData->Bank;
929  foundBankData.EndAddress = bankData->EndAddress;
930  foundBankData.Size += bankData->Size;
931  }
932  else if(bankData->EndAddress == foundBankData.StartAddress)
933  {
934  foundBankData.Bank |= bankData->Bank;
935  foundBankData.StartAddress= bankData->StartAddress;
936  foundBankData.Size += bankData->Size;
937  }
938  }
939 
940  if(foundBankData.Size >= MemorySize)
941  {
942  break;
943  }
944  }
945  else if(bankData->MemoryType == oC_FMC_LLD_MemoryType_SDRAM)
946  {
947  if(Pins->SDNE[0] != oC_Pin_NotUsed || numberOfSDRAMbank > 4 )
948  {
949  /* If this is the first bank that has been found */
950  if(foundBankData.Bank == 0)
951  {
952  foundBankData.Bank = bankData->Bank;
953  foundBankData.StartAddress = bankData->StartAddress;
954  foundBankData.EndAddress = bankData->EndAddress;
955  foundBankData.MemoryType = bankData->MemoryType;
956  foundBankData.Size = bankData->Size;
957  }
958  /* If some bank was found before */
959  else
960  {
961  if(bankData->StartAddress == foundBankData.EndAddress)
962  {
963  foundBankData.Bank |= bankData->Bank;
964  foundBankData.EndAddress = bankData->EndAddress;
965  foundBankData.Size += bankData->Size;
966  }
967  else if(bankData->EndAddress == foundBankData.StartAddress)
968  {
969  foundBankData.Bank |= bankData->Bank;
970  foundBankData.StartAddress= bankData->StartAddress;
971  foundBankData.Size += bankData->Size;
972  }
973  }
974  }
975  else
976  {
977  numberOfSDRAMbank++;
978  }
979 
980  if(foundBankData.Size >= MemorySize)
981  {
982  break;
983  }
984  }
985  }
986  }
987 
988 // foundBankData.StartAddress = BankDatas[12].StartAddress;
989 // foundBankData.EndAddress = BankDatas[12].EndAddress;
990 // foundBankData.Bank = BankDatas[12].Bank;
991 
992  if(foundBankData.Size >= MemorySize)
993  {
994  banks = foundBankData.Bank;
995  *outBanks = banks;
996  *outAddress = foundBankData.StartAddress;
997  }
998 
999  return banks != 0;
1000 }
1001 
1002 //==========================================================================================================================================
1006 //==========================================================================================================================================
1007 static oC_ErrorCode_t UnconfigureSDRAM( const oC_FMC_LLD_SDRAM_Config_t * Config )
1008 {
1009  return oC_ErrorCode_None;
1010 }
1011 
1012 //==========================================================================================================================================
1016 //==========================================================================================================================================
1017 static oC_ErrorCode_t ConnectModulePin( oC_Pin_t Pin , oC_PinFunction_t PinFunction , oC_FMC_LLD_PinUsage_t * PinUsage )
1018 {
1019  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1020  oC_ModulePinIndex_t modulePin = 0;
1021  bool pinUsed = false;
1022 
1023  if(Pin == oC_Pin_NotUsed && (*PinUsage) != oC_FMC_LLD_PinUsage_Required)
1024  {
1025  errorCode = oC_ErrorCode_None;
1026  }
1027  else if(ErrorCondition(oC_GPIO_LLD_IsPinDefined(Pin), oC_ErrorCode_PinNotDefined )
1028  && oC_AssignErrorCode(&errorCode , oC_GPIO_LLD_CheckIsPinUsed(Pin , &pinUsed) )
1029  && ErrorCondition(pinUsed == false , oC_ErrorCode_PinIsUsed )
1030  && oC_AssignErrorCode(&errorCode , oC_GPIO_MSLLD_FindModulePin(Pin , oC_Channel_FMC , PinFunction , &modulePin))
1031  && oC_AssignErrorCode(&errorCode , oC_GPIO_MSLLD_ConnectModulePin(modulePin) )
1032  && oC_AssignErrorCode(&errorCode , oC_GPIO_LLD_SetPinsUsed(Pin) )
1033  )
1034  {
1035  *PinUsage = oC_FMC_LLD_PinUsage_Used;
1036  errorCode = oC_ErrorCode_None;
1037  }
1038 
1039  return errorCode;
1040 }
1041 
1042 //==========================================================================================================================================
1046 //==========================================================================================================================================
1047 static oC_ErrorCode_t DisconnectPin( oC_Pin_t Pin )
1048 {
1049  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1050 
1051  if(
1052  oC_AssignErrorCode(&errorCode , oC_GPIO_MSLLD_SetAlternateNumber(Pin,0) )
1053  && oC_AssignErrorCode(&errorCode , oC_GPIO_LLD_SetPinsUnused(Pin) )
1054  )
1055  {
1056  errorCode = oC_ErrorCode_None;
1057  }
1058 
1059  return errorCode;
1060 }
1061 
1062 //==========================================================================================================================================
1066 //==========================================================================================================================================
1067 static uint32_t TimeToCycles( oC_Time_t Time , oC_Frequency_t Frequency )
1068 {
1069  return (uint32_t)(Time / oC_Frequency_ToTime(Frequency));
1070 }
1071 
1072 //==========================================================================================================================================
1076 //==========================================================================================================================================
1077 static bool SetTimeInCycles( uint32_t * outCycles , oC_Time_t Time , oC_Frequency_t Frequency , uint32_t Min , uint32_t Max , uint32_t Default )
1078 {
1079  bool success = false;
1080  uint32_t cycles = TimeToCycles(Time,Frequency);
1081 
1082  if(Time == 0)
1083  {
1084  *outCycles = Default;
1085  success = true;
1086  }
1087  else if(cycles >= Min && cycles <= Max)
1088  {
1089  *outCycles = cycles;
1090  success = true;
1091  }
1092 
1093  return success;
1094 }
1095 
1096 //==========================================================================================================================================
1100 //==========================================================================================================================================
1101 static bool SendSDRAMCommand( oC_Time_t * Timeout , SDRAMCommand_t * Command , Bank_t Banks )
1102 {
1103  oC_RegisterType_FMC_SDCMR_t SDCMR = { .Value = FMC_SDCMR->Value };
1104 
1105  SDCMR.MRD = Command->ModeRegisterDefinition;
1106  SDCMR.NRFS = Command->AutoRefreshNumber;
1107  SDCMR.CTB1 = (Banks & Bank_MainBank5) ? 1 : 0;
1108  SDCMR.CTB2 = (Banks & Bank_MainBank6) ? 1 : 0;
1109  SDCMR.MODE = Command->CommandMode;
1110 
1111  FMC_SDCMR->Value = SDCMR.Value;
1112 
1113  while(FMC_SDSR->BUSY && (*Timeout) > 0)
1114  {
1115  oC_CLOCK_LLD_DelayForMicroseconds(10);
1116  *Timeout = *Timeout - oC_Time_ToMicroseconds(10);
1117  }
1118 
1119  return FMC_SDSR->BUSY == 0;
1120 }
1121 
1122 //==========================================================================================================================================
1126 //==========================================================================================================================================
1127 static oC_ErrorCode_t CountSDRAMConfigVariables( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , SDRAMConfigVariables_t * outVariables , oC_FMC_LLD_Result_t * outResult )
1128 {
1129  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1130  oC_Frequency_t currentFrequency = oC_CLOCK_LLD_GetClockFrequency();
1131 
1132  outResult->DataBusWidth = (Config->DataBusWidth == 0) ? ChipInfo->SDRAM.DataBusWidth : Config->DataBusWidth;
1133  outResult->DirectAccessProtection = Config->Protection != oC_FMC_LLD_Protection_Default ? Config->Protection :
1134  oC_FMC_LLD_Protection_AllowRead |
1135  oC_FMC_LLD_Protection_AllowWrite;
1136  outVariables->SDCR.SDCLK = ((currentFrequency/2) <= ChipInfo->SDRAM.MaximumClockFrequency) ? 2 :
1137  ((currentFrequency/3) <= ChipInfo->SDRAM.MaximumClockFrequency) ? 3 : 0;
1138 
1139  if(
1140  ErrorCondition( IsDataBusWidthCorrect ( outResult->DataBusWidth) , oC_ErrorCode_DataBusWidthNotCorrect )
1141  && ErrorCondition( IsDataBusWidthSupported( outResult->DataBusWidth) , oC_ErrorCode_DataBusWidthNotSupported )
1142  && ErrorCondition( IsDataBusWidthCorrect ( ChipInfo->SDRAM.DataBusWidth) , oC_ErrorCode_DataBusWidthNotCorrect )
1143  && ErrorCondition( ChipInfo->SDRAM.Size > 0 , oC_ErrorCode_SizeNotCorrect )
1144  && ErrorCondition( ChipInfo->SDRAM.NumberOfRowAddressBits >= 11 , oC_ErrorCode_RowBitsNumberNotSupported )
1145  && ErrorCondition( ChipInfo->SDRAM.NumberOfRowAddressBits <= 13 , oC_ErrorCode_RowBitsNumberNotSupported )
1146  && ErrorCondition( ChipInfo->SDRAM.NumberOfColumnAddressBits >= 8 , oC_ErrorCode_ColumnBitsNumberNotSupported )
1147  && ErrorCondition( ChipInfo->SDRAM.NumberOfColumnAddressBits <= 11 , oC_ErrorCode_ColumnBitsNumberNotSupported )
1148  && ErrorCondition( ChipInfo->SDRAM.NumberOfBanks == 4 || ChipInfo->SDRAM.NumberOfBanks == 2 , oC_ErrorCode_NumberOfBanksNotSupported )
1149  && ErrorCondition( IsProtectionCorrect(outResult->DirectAccessProtection) , oC_ErrorCode_ProtectionNotCorrect )
1150  && ErrorCondition( currentFrequency > 0 , oC_ErrorCode_ClockConfigurationError )
1151  && ErrorCondition( ChipInfo->SDRAM.MaximumClockFrequency > 0 , oC_ErrorCode_WrongFrequency )
1152  && ErrorCondition( ChipInfo->SDRAM.CasLatency > 0 , oC_ErrorCode_CasLatencyNotCorrect )
1153  && ErrorCondition( outVariables->SDCR.SDCLK > 0 , oC_ErrorCode_FrequencyNotPossible )
1154  )
1155  {
1156  oC_Time_t memoryClockPeriod = 0;
1157  oC_Time_t mainClockPeriod = oC_Frequency_ToTime(currentFrequency);
1158  uint32_t activeToReadWriteDelayInCycles = 0;
1159  uint32_t prechargeDelayInCycles = 0;
1160  uint32_t writeRecoveryDelayInCycles = 0;
1161  uint32_t refreshToActivateDelayInCycles = 0;
1162  uint32_t minimumSelfRefreshPeriodInCycles = 0;
1163  uint32_t exitSelfRefreshDelayInCycles = 0;
1164 
1165 
1166  /* If this assertion fails, then the function for verification data bus width does not work correctly (the 0 value is not allowed) */
1167  oC_ASSERT( outResult->DataBusWidth != 0 );
1168 
1169  outResult->ConfiguredFrequency = currentFrequency / ((oC_Frequency_t)outVariables->SDCR.SDCLK);
1170 
1171  /* Memory clock period is required for counting most of parameters */
1172  memoryClockPeriod = oC_Frequency_ToTime(outResult->ConfiguredFrequency);
1173 
1174  /* Size of the used memory can be different than chip size if we do not use all DATA pins */
1175  outResult->MemorySize = ChipInfo->SDRAM.Size;
1176  outResult->MemorySize /= ChipInfo->SDRAM.DataBusWidth / outResult->DataBusWidth;
1177 
1178 
1179  /* Prepare SDCR register value */
1180  outVariables->SDCR.NC = ChipInfo->SDRAM.NumberOfColumnAddressBits - 8;
1181  outVariables->SDCR.NR = ChipInfo->SDRAM.NumberOfRowAddressBits - 11;
1182  outVariables->SDCR.NB = ChipInfo->SDRAM.NumberOfBanks == 4 ? 1 : 0;
1183  outVariables->SDCR.MWID = outResult->DataBusWidth == oC_FMC_LLD_DataBusWidth_8Bits ? 0 :
1184  outResult->DataBusWidth == oC_FMC_LLD_DataBusWidth_16Bits ? 1 :
1185  outResult->DataBusWidth == oC_FMC_LLD_DataBusWidth_32Bits ? 2 : 3;
1186  outVariables->SDCR.CAS = ( memoryClockPeriod * 2 ) >= ChipInfo->SDRAM.CasLatency ? 1 :
1187  ( memoryClockPeriod * 3 ) >= ChipInfo->SDRAM.CasLatency ? 2 :
1188  ( memoryClockPeriod * 4 ) >= ChipInfo->SDRAM.CasLatency ? 3 : 0;
1189  outVariables->SDCR.WP = outResult->DirectAccessProtection & oC_FMC_LLD_Protection_AllowWrite ? 0 : 1;
1190  outVariables->SDCR.RBURST = ChipInfo->SDRAM.Advanced.UseBurstRead ? 1 : 0;
1191  outVariables->SDCR.RPIPE = ( mainClockPeriod * 0 ) >= ChipInfo->SDRAM.Advanced.ReadPipeDelay ? 0 :
1192  ( mainClockPeriod * 2 ) >= ChipInfo->SDRAM.Advanced.ReadPipeDelay ? 1 :
1193  ( mainClockPeriod * 3 ) >= ChipInfo->SDRAM.Advanced.ReadPipeDelay ? 2 : 3;
1194 
1195  CountSDRAMRequiredPins(ChipInfo,outResult);
1196 
1197 
1198  if(
1199  ErrorCondition( outResult->MemorySize > 0 , oC_ErrorCode_SizeNotCorrect )
1200  && ErrorCondition( outResult->MemorySize <= MAX_SDRAM_SIZE , oC_ErrorCode_SizeTooBig )
1201  && ErrorCondition( outVariables->SDCR.CAS > 0 , oC_ErrorCode_CasLatencyNotSupported )
1202  && ErrorCondition( outVariables->SDCR.RPIPE < 3 , oC_ErrorCode_ReadPipeDelayNotPossible )
1203  && ErrorCondition( outVariables->SDCR.MWID < 3 , oC_ErrorCode_DataBusWidthNotCorrect )
1204 
1205  && ErrorCondition( ChipInfo->SDRAM.CyclesToDelayAfterLoadMode >= 1 && ChipInfo->SDRAM.CyclesToDelayAfterLoadMode <= 16 , oC_ErrorCode_DelayNotPossible )
1206  && ErrorCondition( SetTimeInCycles(&activeToReadWriteDelayInCycles , ChipInfo->SDRAM.ActiveToReadWriteDelay , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1207  && ErrorCondition( SetTimeInCycles(&prechargeDelayInCycles , ChipInfo->SDRAM.PrechargeDelay , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1208  && ErrorCondition( SetTimeInCycles(&writeRecoveryDelayInCycles , ChipInfo->SDRAM.WriteRecoveryDelay , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1209  && ErrorCondition( SetTimeInCycles(&refreshToActivateDelayInCycles , ChipInfo->SDRAM.RefreshToActivateDelay , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1210  && ErrorCondition( SetTimeInCycles(&minimumSelfRefreshPeriodInCycles , ChipInfo->SDRAM.MinimumSelfRefreshPeriod , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1211  && ErrorCondition( SetTimeInCycles(&exitSelfRefreshDelayInCycles , ChipInfo->SDRAM.ExitSelfRefreshDelay , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1212 
1213  && ErrorCondition( FindFreeBanks( ChipInfo->MemoryType,
1214  outResult->MemorySize,
1215  &Config->Pins,
1216  (Bank_t*)&outResult->ConfiguredBanks,
1217  &outResult->MemoryStart) , oC_ErrorCode_NoFreeBankAvailable )
1218  )
1219  {
1220  outVariables->SDTR.TRCD = activeToReadWriteDelayInCycles - 1;
1221  outVariables->SDTR.TRP = prechargeDelayInCycles - 1;
1222  outVariables->SDTR.TWR = writeRecoveryDelayInCycles - 1;
1223  outVariables->SDTR.TRC = refreshToActivateDelayInCycles - 1;
1224  outVariables->SDTR.TRAS = minimumSelfRefreshPeriodInCycles - 1;
1225  outVariables->SDTR.TXSR = exitSelfRefreshDelayInCycles - 1;
1226  outVariables->SDTR.TMRD = ChipInfo->SDRAM.CyclesToDelayAfterLoadMode - 1;
1227 
1228  errorCode = oC_ErrorCode_None;
1229  }
1230  }
1231 
1232  return errorCode;
1233 }
1234 
1235 //==========================================================================================================================================
1239 //==========================================================================================================================================
1240 static void CountSDRAMRequiredPins( const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
1241 {
1242  uint32_t numberOfDataBits = outResult->DataBusWidth * 8;
1243 
1244  oC_ASSERT( IsDataBusWidthSupported(outResult->DataBusWidth) );
1245  oC_ASSERT( ChipInfo->SDRAM.NumberOfRowAddressBits >= ChipInfo->SDRAM.NumberOfColumnAddressBits );
1246 
1247  outResult->SDCLK = oC_FMC_LLD_PinUsage_Required;
1248  outResult->SDNWE = oC_FMC_LLD_PinUsage_Required;
1249  outResult->NCAS = oC_FMC_LLD_PinUsage_Required;
1250  outResult->NRAS = oC_FMC_LLD_PinUsage_Required;
1251 
1252  for(uint8_t bitIndex = 0; bitIndex < ChipInfo->SDRAM.NumberOfRowAddressBits; bitIndex++)
1253  {
1254  outResult->A[bitIndex] = oC_FMC_LLD_PinUsage_Required;
1255  }
1256 
1257  for(uint8_t bitIndex = 0; bitIndex < numberOfDataBits ; bitIndex++)
1258  {
1259  outResult->D[bitIndex] = oC_FMC_LLD_PinUsage_Required;
1260  }
1261 
1262  outResult->BA[0] = oC_FMC_LLD_PinUsage_Required;
1263  outResult->BA[1] = ChipInfo->SDRAM.NumberOfBanks == 4 ? oC_FMC_LLD_PinUsage_Required : oC_FMC_LLD_PinUsage_NotUsed;
1264 
1265  outResult->NBL[0] = oC_FMC_LLD_PinUsage_Optional;
1266  outResult->NBL[1] = oC_FMC_LLD_PinUsage_Optional;
1267  outResult->NBL[2] = oC_FMC_LLD_PinUsage_Optional;
1268  outResult->NBL[3] = oC_FMC_LLD_PinUsage_Optional;
1269 
1270  outResult->SDCKE[0] = oC_FMC_LLD_PinUsage_Optional;
1271  outResult->SDCKE[1] = oC_FMC_LLD_PinUsage_Optional;
1272 
1273  outResult->SDNE[0] = oC_FMC_LLD_PinUsage_Optional;
1274  outResult->SDNE[1] = oC_FMC_LLD_PinUsage_Optional;
1275 }
1276 
1277 //==========================================================================================================================================
1281 //==========================================================================================================================================
1282 static oC_ErrorCode_t ConfigureSDRAM(const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , SDRAMConfigVariables_t * outVariables , oC_FMC_LLD_Result_t * outResult )
1283 {
1284  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1285 
1286  if(
1287  ErrorCondition( outVariables->SDCR.SDCLK == 2 || outVariables->SDCR.SDCLK , oC_ErrorCode_MachineSpecificValueNotCorrect )
1288  && ErrorCondition( outResult->ConfiguredBanks & ( Bank_MainBank5 | Bank_MainBank6) , oC_ErrorCode_MachineSpecificValueNotCorrect )
1289  && ErrorCondition( oC_Machine_SetPowerStateForChannel(FMC_Channel,oC_Power_On) , oC_ErrorCode_CannotEnableChannel )
1290  )
1291  {
1292  if(outResult->ConfiguredBanks & Bank_MainBank5)
1293  {
1294  FMC_SDCR1->Value = outVariables->SDCR.Value;
1295  FMC_SDTR1->Value = outVariables->SDTR.Value;
1296 
1297  oC_ASSERT( FMC_SDCR1->Value == outVariables->SDCR.Value );
1298  oC_ASSERT( FMC_SDTR1->Value == outVariables->SDTR.Value );
1299  }
1300  if(outResult->ConfiguredBanks & Bank_MainBank6)
1301  {
1302  FMC_SDCR1->Value = ( outVariables->SDCR.Value & SDRC1_BIT_MASK );
1303  FMC_SDCR2->Value = ( outVariables->SDCR.Value & SDRC2_BIT_MASK );
1304  FMC_SDTR1->Value = ( outVariables->SDTR.Value & SDTR1_BIT_MASK );
1305  FMC_SDTR2->Value = ( outVariables->SDTR.Value & SDTR2_BIT_MASK );
1306 
1307  oC_ASSERT( FMC_SDCR1->Value == ( outVariables->SDCR.Value & SDRC1_BIT_MASK ) );
1308  oC_ASSERT( FMC_SDCR2->Value == ( outVariables->SDCR.Value & SDRC2_BIT_MASK ) );
1309  oC_ASSERT( FMC_SDTR1->Value == ( outVariables->SDTR.Value & SDTR1_BIT_MASK ) );
1310  oC_ASSERT( FMC_SDTR2->Value == ( outVariables->SDTR.Value & SDTR2_BIT_MASK ) );
1311  }
1312  errorCode = oC_ErrorCode_None;
1313  }
1314 
1315  return errorCode;
1316 }
1317 
1318 #undef _________________________________________LOCAL_FUNCTIONS_SECTION____________________________________________________________________
1319 
oC_Power_On
Something is powered on.
Definition: oc_stdtypes.h:252
oc_math.h
Basic math operations.
SDRAMCommand_t::CommandMode
CommandMode_t CommandMode
Command to send.
Definition: oc_fmc_lld.c:171
oC_Frequency_t
double oC_Frequency_t
type to store frequency
Definition: oc_frequency.h:76
oC_Bits_Mask_U32
#define oC_Bits_Mask_U32(FROM, TO)
Definition: oc_bits.h:73
SDRAMCommand_t
stores data for SDRAM commands
Definition: oc_fmc_lld.c:169
oc_lsf.h
The file with interface for LSF module.
oc_mem_lld.h
The file with LLD interface for the MEM driver.
oc_cfg.h
Helper macros for configurations files.
BankData_t::Bank
Bank_t Bank
Bank number mask.
Definition: oc_fmc_lld.c:144
BankData_t::MemoryType
oC_FMC_LLD_MemoryType_t MemoryType
Memory type that bank is designed for.
Definition: oc_fmc_lld.c:145
oc_fmc_lld.h
The file with LLD interface for the FMC driver.
oc_module.h
The file with interface for the module library.
oC_CLOCK_LLD_GetClockFrequency
oC_Frequency_t oC_CLOCK_LLD_GetClockFrequency(void)
returns frequency of the system clock
Definition: oc_clock_lld.c:237
BankData_t::StartAddress
void * StartAddress
Start address of the bank.
Definition: oc_fmc_lld.c:141
BankData_t::EndAddress
void * EndAddress
End address of the bank.
Definition: oc_fmc_lld.c:142
oc_clock_lld.h
The file with LLD interface for the CLOCK driver.
SDRAMConfigVariables_t
stores variables required for SDRAM configuration
Definition: oc_fmc_lld.c:181
BankData_t::Size
oC_UInt_t Size
Size of the bank.
Definition: oc_fmc_lld.c:143
oC_Module_TurnOn
static void oC_Module_TurnOn(oC_Module_t Module)
sets module as turned on
Definition: oc_module.h:170
oc_bits.h
The file with functions for the bits operation.
oC_MCS_EnterCriticalSection
static void oC_MCS_EnterCriticalSection(void)
Enters to critical section.
Definition: oc_mcs.h:755
oc_array.h
Static array definitions.
oc_string.h
The file with interface for string library.
oC_Module_TurnOffVerification
static bool oC_Module_TurnOffVerification(oC_ErrorCode_t *outErrorCode, oC_Module_t Module)
verify if module is turned off
Definition: oc_module.h:155
oC_MCS_ExitCriticalSection
static bool oC_MCS_ExitCriticalSection(void)
Exits from critical section.
Definition: oc_mcs.h:784
oC_Module_TurnOnVerification
static bool oC_Module_TurnOnVerification(oC_ErrorCode_t *outErrorCode, oC_Module_t Module)
verify if module is turned on
Definition: oc_module.h:138
SDRAMCommand_t::AutoRefreshNumber
uint32_t AutoRefreshNumber
Number of auto-refresh.
Definition: oc_fmc_lld.c:172
BankData_t
stores DATA about the bank
Definition: oc_fmc_lld.c:139
SDRAMCommand_t::ModeRegisterDefinition
uint32_t ModeRegisterDefinition
MDR data.
Definition: oc_fmc_lld.c:173
oC_CLOCK_LLD_DelayForMicroseconds
bool oC_CLOCK_LLD_DelayForMicroseconds(oC_UInt_t Microseconds)
perform a delay for us
Definition: oc_clock_lld.c:297
MB
#define MB(MBytes)
Number of MB.
Definition: oc_cfg.h:83
oC_Machine_SetPowerStateForChannel
static bool oC_Machine_SetPowerStateForChannel(oC_Channel_t Channel, oC_Power_t Power)
configures power state for machine channel
Definition: oc_machine.h:593
oc_stdtypes.h
FILE__DESCRIPTION
oC_Module_TurnOff
static void oC_Module_TurnOff(oC_Module_t Module)
sets module as turned off
Definition: oc_module.h:185