Choco OS  V.0.16.9.0
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oc_fmc_chips.c
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1 
27 #include <oc_fmc.h>
28 #include <oc_fmc_chips.h>
29 #include <oc_struct.h>
30 
31 #ifdef oC_FMC_LLD_AVAILABLE
32 
38 #define _________________________________________CHIP_INITIALIZATION_SECTION________________________________________________________________
39 
40 static oC_ErrorCode_t Initialize_MT48LC4M32B2 ( const void * Config , oC_FMC_Context_t Context , oC_Time_t * Timeout );
41 
42 static oC_ErrorCode_t Initialize_IS45S16400J ( const void * Config , oC_FMC_Context_t Context , oC_Time_t * Timeout );
43 
44 #undef _________________________________________CHIP_INITIALIZATION_SECTION________________________________________________________________
45 
46 
47 
53 #define _________________________________________CHIPS_SECTION______________________________________________________________________________
54 
55 //==========================================================================================================================================
59 //==========================================================================================================================================
60 const oC_FMC_ChipInfo_t oC_FMC_ChipInfo_MT48LC4M32B2 = {
61  .ChipParameters.MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
62  .ChipParameters.Name = "MT48LC4M32B2",
63  .ChipParameters.SDRAM.Size = oC_MemorySize_Mb(128),
64  .ChipParameters.SDRAM.BankSize = oC_MemorySize_Mb(32),
65  .ChipParameters.SDRAM.NumberOfBanks = 4,
66  .ChipParameters.SDRAM.DataBusWidth = oC_FMC_LLD_DataBusWidth_32Bits,
67  .ChipParameters.SDRAM.CasLatencyMask = oC_FMC_LLD_SDRAM_CasLatency_1
68  | oC_FMC_LLD_SDRAM_CasLatency_2
69  | oC_FMC_LLD_SDRAM_CasLatency_3 ,
70  .ChipParameters.SDRAM.CasLatency = ns(20) ,
71  .ChipParameters.SDRAM.BurstLengthMask = oC_FMC_LLD_SDRAM_BurstLength_1
72  | oC_FMC_LLD_SDRAM_BurstLength_2
73  | oC_FMC_LLD_SDRAM_BurstLength_4
74  | oC_FMC_LLD_SDRAM_BurstLength_8
75  | oC_FMC_LLD_SDRAM_BurstLength_FullPage ,
76  .ChipParameters.SDRAM.AutoPrechargePossible = true,
77  .ChipParameters.SDRAM.AutoRefreshPossible = true,
78  .ChipParameters.SDRAM.SelfPrechargePossible = true,
79  .ChipParameters.SDRAM.AutoRefreshPeriod = ms(64),
80  .ChipParameters.SDRAM.MaximumClockFrequency = MHz(167) ,
81  .ChipParameters.SDRAM.NumberOfRowAddressBits = 12 ,
82  .ChipParameters.SDRAM.NumberOfColumnAddressBits = 8 ,
83  .ChipParameters.SDRAM.ActiveToReadWriteDelay = ns(20),
84  .ChipParameters.SDRAM.PrechargeDelay = ns(20),
85  .ChipParameters.SDRAM.WriteRecoveryDelay = ns(14),
86  .ChipParameters.SDRAM.RefreshToActivateDelay = ns(70),
87  .ChipParameters.SDRAM.MinimumSelfRefreshPeriod = ns(70),
88  .ChipParameters.SDRAM.ExitSelfRefreshDelay = ns(70),
89  .ChipParameters.SDRAM.CyclesToDelayAfterLoadMode = 2,
90  .ChipParameters.SDRAM.Advanced.ReadPipeDelay = ns(0) ,
91  .ChipParameters.SDRAM.Advanced.UseBurstRead = true ,
92  .InitializationFunction = Initialize_MT48LC4M32B2 ,
93 };
94 
95 const oC_FMC_ChipInfo_t oC_FMC_ChipInfo_IS45S16400J = {
96  .ChipParameters.MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
97  .ChipParameters.Name = "IS45S16400J",
98  .ChipParameters.SDRAM.Size = oC_MemorySize_Mb(64),
99  .ChipParameters.SDRAM.BankSize = oC_MemorySize_Mb(16),
100  .ChipParameters.SDRAM.NumberOfBanks = 4,
101  .ChipParameters.SDRAM.DataBusWidth = oC_FMC_LLD_DataBusWidth_16Bits,
102  .ChipParameters.SDRAM.CasLatencyMask = oC_FMC_LLD_SDRAM_CasLatency_2
103  | oC_FMC_LLD_SDRAM_CasLatency_3,
104  .ChipParameters.SDRAM.CasLatency = ns(40) ,
105  .ChipParameters.SDRAM.BurstLengthMask = oC_FMC_LLD_SDRAM_BurstLength_1
106  | oC_FMC_LLD_SDRAM_BurstLength_2
107  | oC_FMC_LLD_SDRAM_BurstLength_4
108  | oC_FMC_LLD_SDRAM_BurstLength_8
109  | oC_FMC_LLD_SDRAM_BurstLength_FullPage ,
110  .ChipParameters.SDRAM.AutoPrechargePossible = true,
111  .ChipParameters.SDRAM.AutoRefreshPossible = true,
112  .ChipParameters.SDRAM.SelfPrechargePossible = true,
113  .ChipParameters.SDRAM.AutoRefreshPeriod = ms(64),
114  .ChipParameters.SDRAM.MaximumClockFrequency = MHz(133) ,
115  .ChipParameters.SDRAM.NumberOfRowAddressBits = 12 ,
116  .ChipParameters.SDRAM.NumberOfColumnAddressBits = 8 ,
117  .ChipParameters.SDRAM.ActiveToReadWriteDelay = ns(180),
118  .ChipParameters.SDRAM.PrechargeDelay = ns(180),
119  .ChipParameters.SDRAM.WriteRecoveryDelay = ns(180),
120  .ChipParameters.SDRAM.RefreshToActivateDelay = ns(180),
121  .ChipParameters.SDRAM.MinimumSelfRefreshPeriod = ns(180),
122  .ChipParameters.SDRAM.ExitSelfRefreshDelay = ns(180),
123  .ChipParameters.SDRAM.CyclesToDelayAfterLoadMode = 16,
124  .ChipParameters.SDRAM.Advanced.ReadPipeDelay = ns(10) ,
125  .ChipParameters.SDRAM.Advanced.UseBurstRead = true ,
126  .InitializationFunction = Initialize_IS45S16400J ,
127 };
128 
129 
130 #undef _________________________________________CHIPS_SECTION______________________________________________________________________________
131 
137 #define _________________________________________CHIP_INITIALIZATION_FUNCTIONS_SECTION______________________________________________________
138 
139 //==========================================================================================================================================
143 //==========================================================================================================================================
144 static oC_ErrorCode_t Initialize_MT48LC4M32B2( const void * Config , oC_FMC_Context_t Context , oC_Time_t * Timeout )
145 {
146  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
147  oC_FMC_SDRAM_CommandData_t data;
148 
149  oC_Struct_Initialize(data,0);
150 
151  oC_Procedure_Begin
152  {
153  /* 1. Simultaneously apply power to VDD and VDDQ. */
154 
155  /* *
156  * 2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTLcompatible. *
157  * 3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing *
158  * constraints specified for the clock pin. *
159  * *
160  * */
161  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_EnableClock,NULL));
162 
163  /* *
164  * 4. Wait at least 100μs prior to issuing any command other than a COMMAND INHIBIT *
165  * or NOP. *
166  * 5. Starting at some point during this 100μs period, bring CKE HIGH. Continuing at *
167  * least through the end of this period, 1 or more COMMAND INHIBIT or NOP commands *
168  * must be applied. *
169  * */
170  sleep(us(50));
171 
172  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_Nop,NULL));
173 
174  sleep(us(50));
175 
176  /* 6. Perform a PRECHARGE ALL command. */
177  data.Precharge.AllBanks = true;
178  data.Precharge.BankAddress = 0;
179  data.Precharge.Reserved = 0;
180 
181  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_Precharge,&data));
182 
183  /* *
184  * 7. Wait at least tRP time; during this time NOPs or DESELECT commands must be *
185  * given. All banks will complete their precharge, thereby placing the device in the all *
186  * banks idle state. *
187  * */
188  sleep(ns(20));
189 
190  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_Nop,NULL));
191 
192  data.AutoRefresh.NumberOfAutoRefresh = 8;
193  data.AutoRefresh.Reserved = 0;
194  data.AutoRefresh.Reserved2 = false;
195 
196  /* *
197  * 8. Issue an AUTO REFRESH command. *
198  * 9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands *
199  * are allowed *
200  * */
201  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_AutoRefresh,&data));
202 
203  sleep(ns(70));
204 
205  /* *
206  * 10. Issue an AUTO REFRESH command. *
207  * 11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands *
208  * are allowed *
209  * */
210  data.AutoRefresh.NumberOfAutoRefresh = 8;
211 
212  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_AutoRefresh,&data));
213 
214  sleep(ns(70));
215 
216  /*
217  * 12. The SDRAM is now ready for mode register programming. Because the mode register *
218  * will power up in an unknown state, it should be loaded with desired bit values *
219  * prior to applying any operational command. Using the LMR command, program *
220  * the mode register. The mode register is programmed via the MODE REGISTER SET *
221  * command with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed *
222  * again or the device loses power. Not programming the mode register *
223  * upon initialization will result in default settings which may not be desired. Outputs *
224  * are guaranteed High-Z after the LMR command is issued. Outputs should be *
225  * High-Z already before the LMR command is issued. *
226  * */
227  data.LoadModeRegister.AllBanks = true;
228  data.LoadModeRegister.BurstLength = 0;
229  data.LoadModeRegister.BurstType = 0;
230  data.LoadModeRegister.CasLatency = 2;
231  data.LoadModeRegister.OperatingMode = 0;
232  data.LoadModeRegister.WriteBurstMode = 1;
233 
234  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_LoadModeRegister,&data));
235 
236  errorCode = oC_FMC_FinishInitialization(Config,Context);
237  }
238  oC_Procedure_End
239 
240  return errorCode;
241 }
242 
243 static oC_ErrorCode_t Initialize_IS45S16400J( const void * Config , oC_FMC_Context_t Context , oC_Time_t * Timeout )
244 {
245  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
246  oC_FMC_SDRAM_CommandData_t data;
247 
248  oC_Struct_Initialize(data,0);
249 
250  oC_Procedure_Begin
251  {
252  /* 1. Simultaneously apply power to VDD and VDDQ. */
253 
254  /* *
255  * 2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTLcompatible. *
256  * 3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing *
257  * constraints specified for the clock pin. *
258  * *
259  * */
260  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_EnableClock,NULL));
261 
262  /* *
263  * 4. Wait at least 100μs prior to issuing any command other than a COMMAND INHIBIT *
264  * or NOP. *
265  * 5. Starting at some point during this 100μs period, bring CKE HIGH. Continuing at *
266  * least through the end of this period, 1 or more COMMAND INHIBIT or NOP commands *
267  * must be applied. *
268  * */
269  sleep(us(50));
270 
271  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_Nop,NULL));
272 
273  sleep(us(50));
274 
275  /* 6. Perform a PRECHARGE ALL command. */
276  data.Precharge.AllBanks = true;
277  data.Precharge.BankAddress = 0;
278  data.Precharge.Reserved = 0;
279 
280  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_Precharge,&data));
281 
282  /* *
283  * 7. Wait at least tRP time; during this time NOPs or DESELECT commands must be *
284  * given. All banks will complete their precharge, thereby placing the device in the all *
285  * banks idle state. *
286  * */
287  sleep(ns(20));
288 
289  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_Nop,NULL));
290 
291  data.AutoRefresh.NumberOfAutoRefresh = 8;
292  data.AutoRefresh.Reserved = 0;
293  data.AutoRefresh.Reserved2 = false;
294 
295  /* *
296  * 8. Issue an AUTO REFRESH command. *
297  * 9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands *
298  * are allowed *
299  * */
300  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_AutoRefresh,&data));
301 
302  sleep(ns(70));
303 
304  /* *
305  * 10. Issue an AUTO REFRESH command. *
306  * 11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands *
307  * are allowed *
308  * */
309  data.AutoRefresh.NumberOfAutoRefresh = 8;
310 
311  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_AutoRefresh,&data));
312 
313  sleep(ns(70));
314 
315  /*
316  * 12. The SDRAM is now ready for mode register programming. Because the mode register *
317  * will power up in an unknown state, it should be loaded with desired bit values *
318  * prior to applying any operational command. Using the LMR command, program *
319  * the mode register. The mode register is programmed via the MODE REGISTER SET *
320  * command with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed *
321  * again or the device loses power. Not programming the mode register *
322  * upon initialization will result in default settings which may not be desired. Outputs *
323  * are guaranteed High-Z after the LMR command is issued. Outputs should be *
324  * High-Z already before the LMR command is issued. *
325  * */
326  data.LoadModeRegister.AllBanks = true;
327  data.LoadModeRegister.BurstLength = 0;
328  data.LoadModeRegister.BurstType = 0;
329  data.LoadModeRegister.CasLatency = 3;
330  data.LoadModeRegister.OperatingMode = 0;
331  data.LoadModeRegister.WriteBurstMode = 1;
332 
333  oC_Procedure_ExitIfError(oC_FMC_SDRAM_SendCommand(Context,Timeout,oC_FMC_SDRAM_Command_LoadModeRegister,&data));
334 
335  errorCode = oC_FMC_FinishInitialization(Config,Context);
336  }
337  oC_Procedure_End
338 
339  return errorCode;
340 }
341 
342 #undef _________________________________________CHIP_INITIALIZATION_FUNCTIONS_SECTION______________________________________________________
343 
344 #endif /* oC_FMC_LLD_AVAILABLE */
us
#define us(time)
Number of us.
Definition: oc_cfg.h:123
oc_fmc.h
The file with interface for FMC driver.
oC_FMC_SDRAM_Command_Nop
Simple no operation command.
Definition: oc_fmc.h:101
oC_FMC_SDRAM_Command_Precharge
Deactivate a row in a bank (or in all banks)
Definition: oc_fmc.h:106
oC_FMC_SDRAM_CommandData_t
oC_FMC_LLD_SDRAM_CommandData_t oC_FMC_SDRAM_CommandData_t
stores data for SDRAM commands
Definition: oc_fmc.h:121
Initialize_MT48LC4M32B2
static oC_ErrorCode_t Initialize_MT48LC4M32B2(const void *Config, oC_FMC_Context_t Context, oC_Time_t *Timeout)
function that initializes the chip
Definition: oc_fmc_chips.c:144
MHz
#define MHz(Freq)
Number of MHz.
Definition: oc_cfg.h:108
oc_fmc_chips.h
The file with prototypes for chips.
oC_FMC_ChipInfo_MT48LC4M32B2
const oC_FMC_ChipInfo_t oC_FMC_ChipInfo_MT48LC4M32B2
chip informations for MT48LC4M32B2
Definition: oc_fmc_chips.c:60
ms
#define ms(time)
Number of ms.
Definition: oc_cfg.h:128
oc_struct.h
The file with interface for the GPIO driver.
oC_FMC_SDRAM_Command_EnableClock
Enables the clock (provides a stable CLK signal)
Definition: oc_fmc.h:99
ns
#define ns(time)
Number of ns.
Definition: oc_cfg.h:118
oC_FMC_FinishInitialization
oC_ErrorCode_t oC_FMC_FinishInitialization(const oC_FMC_Config_t *Config, oC_FMC_Context_t Context)
finishes initialization
Definition: oc_fmc.c:530
oC_FMC_SDRAM_SendCommand
oC_ErrorCode_t oC_FMC_SDRAM_SendCommand(oC_FMC_Context_t Context, oC_Time_t *Timeout, oC_FMC_SDRAM_Command_t Command, const oC_FMC_SDRAM_CommandData_t *Data)
sends command to SDRAM chips
Definition: oc_fmc.c:468
oC_FMC_ChipInfo_t::ChipParameters
oC_FMC_LLD_ChipParameters_t ChipParameters
Chip parameters.
Definition: oc_fmc.h:160
oC_FMC_ChipInfo_t
stores informations about chip
Definition: oc_fmc.h:158
Context_t
stores ETH context
Definition: oc_eth.c:97
oC_FMC_SDRAM_Command_AutoRefresh
Refreshes a SDRAM.
Definition: oc_fmc.h:108
oC_FMC_SDRAM_Command_LoadModeRegister
Configuration command for loading modes registers.
Definition: oc_fmc.h:102
NULL
#define NULL
pointer to a zero
Definition: oc_null.h:37