Choco OS  V.0.16.9.0
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oc_drivers_cfg.c
1 
27 #include <oc_driverman.h>
28 
34 #define _________________________________________DRIVER_CONFIGURATIONS_SECTION______________________________________________________________
35 
36 #ifdef oC_FMC_LLD_AVAILABLE
37 //==========================================================================================================================================
41 //==========================================================================================================================================
42 static const oC_FMC_Config_t STM32F7Discovery_SDRAMConfig = {
43  .HeapUsage = oC_FMC_HeapUsage_UseAsHeapIfPossible ,
44  .ChipInfo = &oC_FMC_ChipInfo_MT48LC4M32B2 ,
45  .MaximumTimeForConfiguration = s(3) ,
46  .SDRAM.Protection = oC_FMC_Protection_Default ,
47  .SDRAM.Timeout = s(3) ,
48  .SDRAM.DataBusWidth = oC_FMC_LLD_DataBusWidth_16Bits , /* Forcing data bus width to 16 bits */
49  .SDRAM.Pins.SDCLK = oC_Pin_FMC_SDCLK,
50  .SDRAM.Pins.SDCKE[0] = oC_Pin_FMC_SDCKE0,
51  .SDRAM.Pins.SDCKE[1] = oC_Pin_FMC_SDCKE1,
52  .SDRAM.Pins.SDNE[0] = oC_Pin_FMC_SDNE0,
53  .SDRAM.Pins.SDNE[1] = oC_Pin_FMC_SDNE1,
54  .SDRAM.Pins.A[ 0] = oC_Pin_FMC_A0,
55  .SDRAM.Pins.A[ 1] = oC_Pin_FMC_A1,
56  .SDRAM.Pins.A[ 2] = oC_Pin_FMC_A2,
57  .SDRAM.Pins.A[ 3] = oC_Pin_FMC_A3,
58  .SDRAM.Pins.A[ 4] = oC_Pin_FMC_A4,
59  .SDRAM.Pins.A[ 5] = oC_Pin_FMC_A5,
60  .SDRAM.Pins.A[ 6] = oC_Pin_FMC_A6,
61  .SDRAM.Pins.A[ 7] = oC_Pin_FMC_A7,
62  .SDRAM.Pins.A[ 8] = oC_Pin_FMC_A8,
63  .SDRAM.Pins.A[ 9] = oC_Pin_FMC_A9,
64  .SDRAM.Pins.A[10] = oC_Pin_FMC_A10,
65  .SDRAM.Pins.A[11] = oC_Pin_FMC_A11,
66  .SDRAM.Pins.A[12] = oC_Pin_FMC_A12,
67  .SDRAM.Pins.D[ 0] = oC_Pin_FMC_DQ0,
68  .SDRAM.Pins.D[ 1] = oC_Pin_FMC_DQ1,
69  .SDRAM.Pins.D[ 2] = oC_Pin_FMC_DQ2,
70  .SDRAM.Pins.D[ 3] = oC_Pin_FMC_DQ3,
71  .SDRAM.Pins.D[ 4] = oC_Pin_FMC_DQ4,
72  .SDRAM.Pins.D[ 5] = oC_Pin_FMC_DQ5,
73  .SDRAM.Pins.D[ 6] = oC_Pin_FMC_DQ6,
74  .SDRAM.Pins.D[ 7] = oC_Pin_FMC_DQ7,
75  .SDRAM.Pins.D[ 8] = oC_Pin_FMC_DQ8,
76  .SDRAM.Pins.D[ 9] = oC_Pin_FMC_DQ9,
77  .SDRAM.Pins.D[10] = oC_Pin_FMC_DQ10,
78  .SDRAM.Pins.D[11] = oC_Pin_FMC_DQ11,
79  .SDRAM.Pins.D[12] = oC_Pin_FMC_DQ12,
80  .SDRAM.Pins.D[13] = oC_Pin_FMC_DQ13,
81  .SDRAM.Pins.D[14] = oC_Pin_FMC_DQ14,
82  .SDRAM.Pins.D[15] = oC_Pin_FMC_DQ15,
83  .SDRAM.Pins.D[16] = oC_Pin_FMC_DQ16,
84  .SDRAM.Pins.D[17] = oC_Pin_FMC_DQ17,
85  .SDRAM.Pins.D[18] = oC_Pin_FMC_DQ18,
86  .SDRAM.Pins.D[19] = oC_Pin_FMC_DQ19,
87  .SDRAM.Pins.D[20] = oC_Pin_FMC_DQ20,
88  .SDRAM.Pins.D[21] = oC_Pin_FMC_DQ21,
89  .SDRAM.Pins.D[22] = oC_Pin_FMC_DQ22,
90  .SDRAM.Pins.D[23] = oC_Pin_FMC_DQ23,
91  .SDRAM.Pins.D[24] = oC_Pin_FMC_DQ24,
92  .SDRAM.Pins.D[25] = oC_Pin_FMC_DQ25,
93  .SDRAM.Pins.D[26] = oC_Pin_FMC_DQ26,
94  .SDRAM.Pins.D[27] = oC_Pin_FMC_DQ27,
95  .SDRAM.Pins.D[28] = oC_Pin_FMC_DQ28,
96  .SDRAM.Pins.D[29] = oC_Pin_FMC_DQ29,
97  .SDRAM.Pins.D[30] = oC_Pin_FMC_DQ30,
98  .SDRAM.Pins.D[31] = oC_Pin_FMC_DQ31,
99  .SDRAM.Pins.BA[0] = oC_Pin_FMC_BA0,
100  .SDRAM.Pins.BA[1] = oC_Pin_FMC_BA1,
101  .SDRAM.Pins.BA[2] = oC_Pin_FMC_BA2,
102  .SDRAM.Pins.BA[3] = oC_Pin_FMC_BA3,
103  .SDRAM.Pins.NRAS = oC_Pin_FMC_SDNRAS,
104  .SDRAM.Pins.NCAS = oC_Pin_FMC_SDNCAS,
105  .SDRAM.Pins.SDNWE = oC_Pin_FMC_SDNWE,
106  .SDRAM.Pins.NBL[0] = oC_Pin_FMC_NBL0,
107  .SDRAM.Pins.NBL[1] = oC_Pin_FMC_NBL1,
108  .SDRAM.Pins.NBL[2] = oC_Pin_FMC_NBL2,
109  .SDRAM.Pins.NBL[3] = oC_Pin_FMC_NBL3,
110 };
111 
112 static const oC_FMC_Config_t STM32F4Discovery_SDRAMConfig = {
113  .HeapUsage = oC_FMC_HeapUsage_UseAsHeapIfPossible ,
114  .ChipInfo = &oC_FMC_ChipInfo_IS45S16400J ,
115  .MaximumTimeForConfiguration = s(3) ,
116  .SDRAM.Protection = oC_FMC_Protection_Default ,
117  .SDRAM.Timeout = s(3) ,
118  .SDRAM.DataBusWidth = oC_FMC_LLD_DataBusWidth_16Bits , /* Forcing data bus width to 16 bits */
119  .SDRAM.Pins.SDCLK = oC_Pin_FMC_SDCLK,
120  .SDRAM.Pins.SDCKE[0] = oC_Pin_FMC_SDCKE0,
121  .SDRAM.Pins.SDCKE[1] = oC_Pin_FMC_SDCKE1,
122  .SDRAM.Pins.SDNE[0] = oC_Pin_FMC_SDNE0,
123  .SDRAM.Pins.SDNE[1] = oC_Pin_FMC_SDNE1,
124  .SDRAM.Pins.A[ 0] = oC_Pin_FMC_A0,
125  .SDRAM.Pins.A[ 1] = oC_Pin_FMC_A1,
126  .SDRAM.Pins.A[ 2] = oC_Pin_FMC_A2,
127  .SDRAM.Pins.A[ 3] = oC_Pin_FMC_A3,
128  .SDRAM.Pins.A[ 4] = oC_Pin_FMC_A4,
129  .SDRAM.Pins.A[ 5] = oC_Pin_FMC_A5,
130  .SDRAM.Pins.A[ 6] = oC_Pin_FMC_A6,
131  .SDRAM.Pins.A[ 7] = oC_Pin_FMC_A7,
132  .SDRAM.Pins.A[ 8] = oC_Pin_FMC_A8,
133  .SDRAM.Pins.A[ 9] = oC_Pin_FMC_A9,
134  .SDRAM.Pins.A[10] = oC_Pin_FMC_A10,
135  .SDRAM.Pins.A[11] = oC_Pin_FMC_A11,
136  .SDRAM.Pins.A[12] = oC_Pin_FMC_A12,
137  .SDRAM.Pins.D[ 0] = oC_Pin_FMC_DQ0,
138  .SDRAM.Pins.D[ 1] = oC_Pin_FMC_DQ1,
139  .SDRAM.Pins.D[ 2] = oC_Pin_FMC_DQ2,
140  .SDRAM.Pins.D[ 3] = oC_Pin_FMC_DQ3,
141  .SDRAM.Pins.D[ 4] = oC_Pin_FMC_DQ4,
142  .SDRAM.Pins.D[ 5] = oC_Pin_FMC_DQ5,
143  .SDRAM.Pins.D[ 6] = oC_Pin_FMC_DQ6,
144  .SDRAM.Pins.D[ 7] = oC_Pin_FMC_DQ7,
145  .SDRAM.Pins.D[ 8] = oC_Pin_FMC_DQ8,
146  .SDRAM.Pins.D[ 9] = oC_Pin_FMC_DQ9,
147  .SDRAM.Pins.D[10] = oC_Pin_FMC_DQ10,
148  .SDRAM.Pins.D[11] = oC_Pin_FMC_DQ11,
149  .SDRAM.Pins.D[12] = oC_Pin_FMC_DQ12,
150  .SDRAM.Pins.D[13] = oC_Pin_FMC_DQ13,
151  .SDRAM.Pins.D[14] = oC_Pin_FMC_DQ14,
152  .SDRAM.Pins.D[15] = oC_Pin_FMC_DQ15,
153  .SDRAM.Pins.D[16] = oC_Pin_FMC_DQ16,
154  .SDRAM.Pins.D[17] = oC_Pin_FMC_DQ17,
155  .SDRAM.Pins.D[18] = oC_Pin_FMC_DQ18,
156  .SDRAM.Pins.D[19] = oC_Pin_FMC_DQ19,
157  .SDRAM.Pins.D[20] = oC_Pin_FMC_DQ20,
158  .SDRAM.Pins.D[21] = oC_Pin_FMC_DQ21,
159  .SDRAM.Pins.D[22] = oC_Pin_FMC_DQ22,
160  .SDRAM.Pins.D[23] = oC_Pin_FMC_DQ23,
161  .SDRAM.Pins.D[24] = oC_Pin_FMC_DQ24,
162  .SDRAM.Pins.D[25] = oC_Pin_FMC_DQ25,
163  .SDRAM.Pins.D[26] = oC_Pin_FMC_DQ26,
164  .SDRAM.Pins.D[27] = oC_Pin_FMC_DQ27,
165  .SDRAM.Pins.D[28] = oC_Pin_FMC_DQ28,
166  .SDRAM.Pins.D[29] = oC_Pin_FMC_DQ29,
167  .SDRAM.Pins.D[30] = oC_Pin_FMC_DQ30,
168  .SDRAM.Pins.D[31] = oC_Pin_FMC_DQ31,
169  .SDRAM.Pins.BA[0] = oC_Pin_FMC_BA0,
170  .SDRAM.Pins.BA[1] = oC_Pin_FMC_BA1,
171  .SDRAM.Pins.BA[2] = oC_Pin_FMC_BA2,
172  .SDRAM.Pins.BA[3] = oC_Pin_FMC_BA3,
173  .SDRAM.Pins.NRAS = oC_Pin_FMC_SDNRAS,
174  .SDRAM.Pins.NCAS = oC_Pin_FMC_SDNCAS,
175  .SDRAM.Pins.SDNWE = oC_Pin_FMC_SDNWE,
176  .SDRAM.Pins.NBL[0] = oC_Pin_FMC_NBL0,
177  .SDRAM.Pins.NBL[1] = oC_Pin_FMC_NBL1,
178  .SDRAM.Pins.NBL[2] = oC_Pin_FMC_NBL2,
179  .SDRAM.Pins.NBL[3] = oC_Pin_FMC_NBL3,
180 };
181 
182 #endif
183 #undef _________________________________________DRIVER_CONFIGURATIONS_SECTION______________________________________________________________
184 
185 //==========================================================================================================================================
192 //==========================================================================================================================================
193 #define CFG_AUTO_CONFIGURATION_LIST(ADD_CONFIGURATION,DONT_ADD_CONFIGURATION) \
194  DONT_ADD_CONFIGURATION( FMC , STM32F7Discovery_SDRAMConfig )\
195  DONT_ADD_CONFIGURATION( FMC , STM32F4Discovery_SDRAMConfig )\
196 
197 
198 
s
#define s(time)
Number of s.
Definition: oc_cfg.h:133
oC_FMC_ChipInfo_MT48LC4M32B2
const oC_FMC_ChipInfo_t oC_FMC_ChipInfo_MT48LC4M32B2
chip informations for MT48LC4M32B2
Definition: oc_fmc_chips.c:60
oC_FMC_Protection_Default
Default protection for the memory type.
Definition: oc_fmc.h:66
oc_driverman.h
The file with drivers manager interface.
oC_FMC_HeapUsage_UseAsHeapIfPossible
Default option - if usage of heap is possible, then use it.
Definition: oc_fmc.h:83
oC_FMC_Config_t::HeapUsage
oC_FMC_HeapUsage_t HeapUsage
Use or not the configured memory as heap.
Definition: oc_fmc.h:178
oC_FMC_Config_t
FMC driver configuration structure.
Definition: oc_fmc.h:176