Choco OS  V.0.16.9.0
Join to the chocolate world
oc_fmc_lld.c
1 
29 #include <oc_fmc_lld.h>
30 #include <oc_mem_lld.h>
31 #include <oc_bits.h>
32 #include <oc_module.h>
33 #include <oc_lsf.h>
34 #include <oc_stdtypes.h>
35 #include <oc_cfg.h>
36 #include <oc_array.h>
37 #include <oc_gpio_mslld.h>
38 #include <oc_math.h>
39 #include <oc_clock_lld.h>
40 #include <oc_string.h>
41 
47 #define _________________________________________MACROS_SECTION_____________________________________________________________________________
48 
49 #define IsRam(Address) (oC_LSF_IsRamAddress(Address) || oC_LSF_IsExternalAddress(Address))
50 #define IsRom(Address) oC_LSF_IsRomAddress(Address)
51 #define IsExternal(Address) oC_LSF_IsExternalAddress(Address)
52 #define IsAddressCorrect(Address) IsRam(Address) || IsRom(Address)
53 #define IsChannelPoweredOn() (oC_Machine_GetPowerStateForChannel(Channel) == oC_Power_On)
54 #define IsBankUsed(Bank) ((BanksUsage & ((Bank) & Bank_MainBankMask)) != 0)
55 #define GetNumberOfPinsInStructure(PinsType) ( (sizeof(PinsType)) / sizeof(oC_Pin_t) )
56 #define SetBankUsed(Bank) BanksUsage |= (Bank)
57 #define SetBankUnused(Bank) BanksUsage &= ~(Bank)
58 #define FMC_Channel oC_Channel_FMC
59 #define MAX_MEMORY_SIZE oC_MemorySize_MB(512)
60 #define MAX_SDRAM_SIZE oC_MemorySize_MB(512)
61 #define FMC_BCR1 oC_Register(FMC,FMC_BCR1)
62 #define FMC_BCR2 oC_Register(FMC,FMC_BCR2)
63 #define FMC_BCR3 oC_Register(FMC,FMC_BCR3)
64 #define FMC_BCR4 oC_Register(FMC,FMC_BCR4)
65 #define FMC_BTR1 oC_Register(FMC,FMC_BTR1)
66 #define FMC_BTR2 oC_Register(FMC,FMC_BTR2)
67 #define FMC_BTR3 oC_Register(FMC,FMC_BTR3)
68 #define FMC_BTR4 oC_Register(FMC,FMC_BTR4)
69 #define FMC_BWTR1 oC_Register(FMC,FMC_BWTR1)
70 #define FMC_BWTR2 oC_Register(FMC,FMC_BWTR2)
71 #define FMC_BWTR3 oC_Register(FMC,FMC_BWTR3)
72 #define FMC_BWTR4 oC_Register(FMC,FMC_BWTR4)
73 #define FMC_PCR oC_Register(FMC,FMC_PCR)
74 #define FMC_SR oC_Register(FMC,FMC_SR)
75 #define FMC_PMEM oC_Register(FMC,FMC_PMEM)
76 #define FMC_PATT oC_Register(FMC,FMC_PATT)
77 #define FMC_ECCR oC_Register(FMC,FMC_ECCR)
78 #define FMC_SDCR1 oC_Register(FMC,FMC_SDCR1)
79 #define FMC_SDCR2 oC_Register(FMC,FMC_SDCR2)
80 #define FMC_SDTR1 oC_Register(FMC,FMC_SDTR1)
81 #define FMC_SDTR2 oC_Register(FMC,FMC_SDTR2)
82 #define FMC_SDCMR oC_Register(FMC,FMC_SDCMR)
83 #define FMC_SDRTR oC_Register(FMC,FMC_SDRTR)
84 #define FMC_SDSR oC_Register(FMC,FMC_SDSR)
85 
86 #undef _________________________________________MACROS_SECTION_____________________________________________________________________________
87 
93 #define _________________________________________TYPES_SECTION______________________________________________________________________________
94 
95 //==========================================================================================================================================
99 //==========================================================================================================================================
100 typedef enum
101 {
102  Bank_SubBankMask = 0xF ,
103  Bank_SubBank1 = (1<<0) ,
104  Bank_SubBank2 = (1<<1) ,
105  Bank_SubBank3 = (1<<2) ,
106  Bank_SubBank4 = (1<<3) ,
107  Bank_MainBankMask = 0xF0 ,
108  Bank_MainBank1 = (1<<4) ,
109  Bank_MainBank3 = (1<<5) ,
110  Bank_MainBank5 = (1<<6) ,
111  Bank_MainBank6 = (1<<7) ,
112  Bank_1_NOR_PSRAM1 = Bank_MainBank1 | Bank_SubBank1 ,
113  Bank_1_NOR_PSRAM2 = Bank_MainBank1 | Bank_SubBank2 ,
114  Bank_1_NOR_PSRAM3 = Bank_MainBank1 | Bank_SubBank3 ,
115  Bank_1_NOR_PSRAM4 = Bank_MainBank1 | Bank_SubBank4 ,
116  Bank_3_NAND_FlashMemory1 = Bank_MainBank3 | Bank_SubBank1 ,
117  Bank_3_NAND_FlashMemory2 = Bank_MainBank3 | Bank_SubBank2 ,
118  Bank_3_NAND_FlashMemory3 = Bank_MainBank3 | Bank_SubBank3 ,
119  Bank_3_NAND_FlashMemory4 = Bank_MainBank3 | Bank_SubBank4 ,
120  Bank_5_SDRAM1 = Bank_MainBank5 | Bank_SubBank1 ,
121  Bank_5_SDRAM2 = Bank_MainBank5 | Bank_SubBank2 ,
122  Bank_5_SDRAM3 = Bank_MainBank5 | Bank_SubBank3 ,
123  Bank_5_SDRAM4 = Bank_MainBank5 | Bank_SubBank4 ,
124  Bank_6_SDRAM1 = Bank_MainBank6 | Bank_SubBank1 ,
125  Bank_6_SDRAM2 = Bank_MainBank6 | Bank_SubBank2 ,
126  Bank_6_SDRAM3 = Bank_MainBank6 | Bank_SubBank3 ,
127  Bank_6_SDRAM4 = Bank_MainBank6 | Bank_SubBank4 ,
128 } Bank_t;
129 
130 //==========================================================================================================================================
134 //==========================================================================================================================================
135 typedef struct
136 {
137  void * StartAddress;
138  void * EndAddress;
139  oC_UInt_t Size;
140  Bank_t Bank;
141  oC_FMC_LLD_MemoryType_t MemoryType;
142 } BankData_t;
143 
144 //==========================================================================================================================================
148 //==========================================================================================================================================
149 typedef enum
150 {
151  CommandMode_NormalMode ,
152  CommandMode_ClockConfigurationEnable ,
153  CommandMode_AllBankPrecharge ,
154  CommandMode_AutoRefresh ,
155  CommandMode_LoadModeRegister ,
156  CommandMode_SelfRefresh ,
157  CommandMode_PowerDown
158 } CommandMode_t;
159 
160 //==========================================================================================================================================
164 //==========================================================================================================================================
165 typedef struct
166 {
167  CommandMode_t CommandMode;
168  uint32_t AutoRefreshNumber;
169  uint32_t ModeRegisterDefinition;
170 } SDRAMCommand_t;
171 
172 //==========================================================================================================================================
176 //==========================================================================================================================================
177 typedef struct
178 {
179  oC_RegisterType_FMC_SDCR1_t SDCR;
180  oC_RegisterType_FMC_SDTR1_t SDTR;
181 } SDRAMConfigVariables_t;
182 
183 #undef _________________________________________TYPES_SECTION______________________________________________________________________________
184 
185 
191 #define _________________________________________VARIABLES_SECTION__________________________________________________________________________
192 
193 static Bank_t BanksUsage = 0;
194 static const BankData_t BankDatas[] = {
195  /* =========================== BANK 1 ============================== */
196  {
197  .Bank = Bank_1_NOR_PSRAM1 ,
198  .MemoryType = oC_FMC_LLD_MemoryType_NOR_Flash | oC_FMC_LLD_MemoryType_PSRAM ,
199  .StartAddress = (void*)0x60000000 ,
200  .EndAddress = (void*)0x64000000 ,
201  .Size = MB(64)
202  } ,
203  {
204  .Bank = Bank_1_NOR_PSRAM2 ,
205  .MemoryType = oC_FMC_LLD_MemoryType_NOR_Flash | oC_FMC_LLD_MemoryType_PSRAM ,
206  .StartAddress = (void*)0x64000000 ,
207  .EndAddress = (void*)0x68000000 ,
208  .Size = MB(64)
209  } ,
210  {
211  .Bank = Bank_1_NOR_PSRAM3 ,
212  .MemoryType = oC_FMC_LLD_MemoryType_NOR_Flash | oC_FMC_LLD_MemoryType_PSRAM ,
213  .StartAddress = (void*)0x68000000 ,
214  .EndAddress = (void*)0x6C000000 ,
215  .Size = MB(64)
216  } ,
217  {
218  .Bank = Bank_1_NOR_PSRAM4 ,
219  .MemoryType = oC_FMC_LLD_MemoryType_NOR_Flash | oC_FMC_LLD_MemoryType_PSRAM ,
220  .StartAddress = (void*)0x6C000000 ,
221  .EndAddress = (void*)0x70000000 ,
222  .Size = MB(64)
223  } ,
224  /* =========================== BANK 3 ============================== */
225  {
226  .Bank = Bank_3_NAND_FlashMemory1 ,
227  .MemoryType = oC_FMC_LLD_MemoryType_NAND_Flash ,
228  .StartAddress = (void*)0x80000000 ,
229  .EndAddress = (void*)0x84000000 ,
230  .Size = MB(64)
231  } ,
232  {
233  .Bank = Bank_3_NAND_FlashMemory2 ,
234  .MemoryType = oC_FMC_LLD_MemoryType_NAND_Flash ,
235  .StartAddress = (void*)0x84000000 ,
236  .EndAddress = (void*)0x88000000 ,
237  .Size = MB(64)
238  } ,
239  {
240  .Bank = Bank_3_NAND_FlashMemory3 ,
241  .MemoryType = oC_FMC_LLD_MemoryType_NAND_Flash ,
242  .StartAddress = (void*)0x88000000 ,
243  .EndAddress = (void*)0x8C000000 ,
244  .Size = MB(64)
245  } ,
246  {
247  .Bank = Bank_3_NAND_FlashMemory4 ,
248  .MemoryType = oC_FMC_LLD_MemoryType_NAND_Flash ,
249  .StartAddress = (void*)0x8C000000 ,
250  .EndAddress = (void*)0x90000000 ,
251  .Size = MB(64)
252  } ,
253  /* =========================== BANK 5 ============================== */
254  {
255  .Bank = Bank_5_SDRAM1 ,
256  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
257  .StartAddress = (void*)0xC0000000 ,
258  .EndAddress = (void*)0xC4000000 ,
259  .Size = MB(64)
260  } ,
261  {
262  .Bank = Bank_5_SDRAM2 ,
263  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
264  .StartAddress = (void*)0xC4000000 ,
265  .EndAddress = (void*)0xC8000000 ,
266  .Size = MB(64)
267  } ,
268  {
269  .Bank = Bank_5_SDRAM3 ,
270  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
271  .StartAddress = (void*)0xC8000000 ,
272  .EndAddress = (void*)0xCC000000 ,
273  .Size = MB(64)
274  } ,
275  {
276  .Bank = Bank_5_SDRAM4 ,
277  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
278  .StartAddress = (void*)0xCC000000 ,
279  .EndAddress = (void*)0xD0000000 ,
280  .Size = MB(64)
281  } ,
282  /* =========================== BANK 6 ============================== */
283  {
284  .Bank = Bank_6_SDRAM1 ,
285  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
286  .StartAddress = (void*)0xD0000000 ,
287  .EndAddress = (void*)0xD4000000 ,
288  .Size = MB(64)
289  } ,
290  {
291  .Bank = Bank_6_SDRAM2 ,
292  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
293  .StartAddress = (void*)0xD4000000 ,
294  .EndAddress = (void*)0xD8000000 ,
295  .Size = MB(64)
296  } ,
297  {
298  .Bank = Bank_6_SDRAM3 ,
299  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
300  .StartAddress = (void*)0xD8000000 ,
301  .EndAddress = (void*)0xDC000000 ,
302  .Size = MB(64)
303  } ,
304  {
305  .Bank = Bank_6_SDRAM4 ,
306  .MemoryType = oC_FMC_LLD_MemoryType_SDRAM ,
307  .StartAddress = (void*)0xDC000000 ,
308  .EndAddress = (void*)0xE0000000 ,
309  .Size = MB(64)
310  } ,
311 };
312 
313 
314 #undef _________________________________________VARIABLES_SECTION__________________________________________________________________________
315 
321 #define _________________________________________LOCAL_PROTOTYPES_SECTION___________________________________________________________________
322 
323 static inline bool IsProtectionCorrect ( oC_FMC_LLD_Protection_t Protection );
324 static inline bool IsDataBusWidthCorrect ( oC_FMC_LLD_DataBusWidth_t DataBusWidth );
325 static inline bool IsDataBusWidthSupported ( oC_FMC_LLD_DataBusWidth_t DataBusWidth );
326 static oC_ErrorCode_t ConnectSDRAMModulePins ( const oC_FMC_LLD_SDRAM_Pins_t * Pins , oC_FMC_LLD_Result_t * Result );
327 static oC_ErrorCode_t DisconnectModulePins ( const oC_Pin_t * Pins , oC_FMC_LLD_PinUsage_t * PinsUsage , oC_UInt_t NumberOfPins );
328 static bool FindFreeBanks ( oC_FMC_LLD_MemoryType_t MemoryType , oC_MemorySize_t MemorySize , Bank_t * outBanks , uint8_t ** outAddress );
329 static oC_ErrorCode_t ConfigureSDRAM ( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , SDRAMConfigVariables_t * outVariables , oC_FMC_LLD_Result_t * outResult );
330 static oC_ErrorCode_t UnconfigureSDRAM ( const oC_FMC_LLD_SDRAM_Config_t * Config );
331 static oC_ErrorCode_t ConnectModulePin ( oC_Pin_t Pin , oC_PinFunction_t PinFunction , oC_FMC_LLD_PinUsage_t * PinUsage);
332 static oC_ErrorCode_t DisconnectPin ( oC_Pin_t Pin );
333 static uint32_t TimeToCycles ( oC_Time_t Time , oC_Frequency_t Frequency );
334 static bool SetTimeInCycles ( uint32_t * outCycles , oC_Time_t Time , oC_Frequency_t Frequency , uint32_t Min , uint32_t Max , uint32_t Default );
335 static bool SendSDRAMCommand ( oC_Time_t * Timeout , SDRAMCommand_t * Command , Bank_t Banks );
336 static oC_ErrorCode_t CountSDRAMConfigVariables ( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , SDRAMConfigVariables_t * outVariables , oC_FMC_LLD_Result_t * outResult );
337 static void CountSDRAMRequiredPins ( const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult );
338 
339 #undef _________________________________________LOCAL_PROTOTYPES_SECTION___________________________________________________________________
340 
341 
347 #define _________________________________________FUNCTIONS_SECTION__________________________________________________________________________
348 
349 //==========================================================================================================================================
354 //==========================================================================================================================================
355 oC_ErrorCode_t oC_FMC_LLD_TurnOnDriver( void )
356 {
357  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
358 
359  oC_MCS_EnterCriticalSection();
360 
361  if(oC_Module_TurnOffVerification(&errorCode , oC_Module_FMC_LLD))
362  {
363  oC_Module_TurnOn(oC_Module_FMC_LLD);
364  BanksUsage = 0;
365  errorCode = oC_ErrorCode_None;
366  }
367 
368  oC_MCS_ExitCriticalSection();
369 
370  return errorCode;
371 }
372 
373 //==========================================================================================================================================
378 //==========================================================================================================================================
379 oC_ErrorCode_t oC_FMC_LLD_TurnOffDriver( void )
380 {
381  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
382 
383  oC_MCS_EnterCriticalSection();
384 
385  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_FMC_LLD))
386  {
387  oC_Module_TurnOff(oC_Module_FMC_LLD);
388  errorCode = oC_ErrorCode_None;
389  }
390 
391  oC_MCS_ExitCriticalSection();
392 
393  return errorCode;
394 }
395 
396 //==========================================================================================================================================
401 //==========================================================================================================================================
402 oC_ErrorCode_t oC_FMC_LLD_ConfigureSDRAM( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
403 {
404  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
405  SDRAMConfigVariables_t configVariables;
406 
407  memset(&configVariables,0,sizeof(configVariables));
408 
409  if(oC_Module_TurnOnVerification(&errorCode,oC_Module_FMC_LLD))
410  {
411  oC_MCS_EnterCriticalSection();
412 
413  if(
414  ErrorCondition( IsAddressCorrect(Config) , oC_ErrorCode_WrongConfigAddress )
415  && ErrorCondition( IsAddressCorrect(ChipInfo) , oC_ErrorCode_WrongAddress )
416  && ErrorCondition( IsRam(outResult) , oC_ErrorCode_OutputAddressNotInRAM )
417  && ErrorCondition( ChipInfo->MemoryType == oC_FMC_LLD_MemoryType_SDRAM , oC_ErrorCode_MemoryTypeNotCorrect )
418  )
419  {
420  if(
421  oC_AssignErrorCode(&errorCode , CountSDRAMConfigVariables( Config , ChipInfo, &configVariables , outResult ))
422  && oC_AssignErrorCode(&errorCode , ConnectSDRAMModulePins ( &Config->Pins , outResult ))
423  && oC_AssignErrorCode(&errorCode , ConfigureSDRAM ( Config , ChipInfo, &configVariables , outResult ))
424  )
425  {
426  SetBankUsed(outResult->ConfiguredBanks);
427  errorCode = oC_ErrorCode_None;
428  }
429  else
430  {
431  memset(outResult,0,sizeof(oC_FMC_LLD_Result_t));
432  }
433  }
434 
435  oC_MCS_ExitCriticalSection();
436  }
437 
438  return errorCode;
439 }
440 
441 //==========================================================================================================================================
446 //==========================================================================================================================================
447 oC_ErrorCode_t oC_FMC_LLD_ConfigureNORFlash( const oC_FMC_LLD_NORFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
448 {
449  return oC_ErrorCode_NotImplemented;
450 }
451 
452 //==========================================================================================================================================
457 //==========================================================================================================================================
458 oC_ErrorCode_t oC_FMC_LLD_ConfigureNANDFlash(const oC_FMC_LLD_NANDFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
459 {
460  return oC_ErrorCode_NotImplemented;
461 }
462 
463 //==========================================================================================================================================
468 //==========================================================================================================================================
469 oC_ErrorCode_t oC_FMC_LLD_ConfigurePSRAM( const oC_FMC_LLD_PSRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
470 {
471  return oC_ErrorCode_NotImplemented;
472 }
473 
474 //==========================================================================================================================================
479 //==========================================================================================================================================
480 oC_ErrorCode_t oC_FMC_LLD_UnconfigureSDRAM( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
481 {
482  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
483 
484  if(oC_Module_TurnOnVerification(&errorCode , oC_Module_FMC_LLD))
485  {
486  if(
487  ErrorCondition( IsRam(Config) || IsRom(Config) , oC_ErrorCode_WrongConfigAddress ) &&
488  ErrorCondition( IsRam(outResult) , oC_ErrorCode_OutputAddressNotInRAM )
489  )
490  {
491  oC_MCS_EnterCriticalSection();
492 
493  if(
494  oC_AssignErrorCode(&errorCode , DisconnectModulePins(Config->Pins.PinsArray,outResult->PinsUsage,GetNumberOfPinsInStructure(oC_FMC_LLD_SDRAM_Pins_t)) ) &&
495  oC_AssignErrorCode(&errorCode , UnconfigureSDRAM(Config) )
496  )
497  {
498  SetBankUnused(outResult->ConfiguredBanks);
499  errorCode = oC_ErrorCode_None;
500  }
501 
502  oC_MCS_ExitCriticalSection();
503  }
504  }
505 
506  return errorCode;
507 }
508 
509 //==========================================================================================================================================
514 //==========================================================================================================================================
515 oC_ErrorCode_t oC_FMC_LLD_UnconfigureNORFlash( const oC_FMC_LLD_NORFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
516 {
517  return oC_ErrorCode_NotImplemented;
518 }
519 
520 //==========================================================================================================================================
525 //==========================================================================================================================================
526 oC_ErrorCode_t oC_FMC_LLD_UnconfigureNANDFlash(const oC_FMC_LLD_NANDFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
527 {
528  return oC_ErrorCode_NotImplemented;
529 }
530 
531 //==========================================================================================================================================
536 //==========================================================================================================================================
537 oC_ErrorCode_t oC_FMC_LLD_UnconfigurePSRAM( const oC_FMC_LLD_PSRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
538 {
539  return oC_ErrorCode_NotImplemented;
540 }
541 
542 //==========================================================================================================================================
547 //==========================================================================================================================================
548 oC_ErrorCode_t oC_FMC_LLD_SendSDRAMCommand( oC_FMC_LLD_Result_t * Result , oC_Time_t * Timeout , oC_FMC_LLD_SDRAM_Command_t Command , const oC_FMC_LLD_SDRAM_CommandData_t * Data )
549 {
550  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
551 
552  if(
553  oC_Module_TurnOnVerification(&errorCode , oC_Module_FMC_LLD ) &&
554  ErrorCondition( IsRam(Result) , oC_ErrorCode_WrongAddress )
555  )
556  {
557  bool sendCommand = false;
558  SDRAMCommand_t command = {0};
559 
560  switch(Command)
561  {
562  case oC_FMC_LLD_SDRAM_Command_EnableClock:
563  command.CommandMode = CommandMode_ClockConfigurationEnable;
564  command.AutoRefreshNumber = 1;
565  command.ModeRegisterDefinition = 0;
566  sendCommand = true;
567  errorCode = oC_ErrorCode_None;
568  break;
569  case oC_FMC_LLD_SDRAM_Command_Inhibit :
570  sendCommand = false;
571  errorCode = oC_ErrorCode_None;
572  break;
573  case oC_FMC_LLD_SDRAM_Command_Nop :
574  sendCommand = false;
575  errorCode = oC_ErrorCode_None;
576  break;
577  case oC_FMC_LLD_SDRAM_Command_LoadModeRegister:
578  if(ErrorCondition(IsRam(Data) || IsRom(Data) , oC_ErrorCode_WrongAddress))
579  {
580  command.CommandMode = CommandMode_LoadModeRegister;
581  command.AutoRefreshNumber = 1;
582  command.ModeRegisterDefinition = Data->LoadModeRegister.MRD;
583  sendCommand = true;
584  errorCode = oC_ErrorCode_None;
585  }
586  break;
587  case oC_FMC_LLD_SDRAM_Command_Active:
588  errorCode = oC_ErrorCode_NotImplemented;
589  break;
590  case oC_FMC_LLD_SDRAM_Command_Read:
591  errorCode = oC_ErrorCode_NotImplemented;
592  break;
593  case oC_FMC_LLD_SDRAM_Command_Write:
594  errorCode = oC_ErrorCode_NotImplemented;
595  break;
596  case oC_FMC_LLD_SDRAM_Command_Precharge:
597  if(ErrorCondition(IsRam(Data) || IsRom(Data) , oC_ErrorCode_WrongAddress))
598  {
599  command.CommandMode = CommandMode_AllBankPrecharge;
600  command.AutoRefreshNumber = 1;
601  command.ModeRegisterDefinition = 0;
602  sendCommand = true;
603  errorCode = oC_ErrorCode_None;
604  }
605  break;
606  case oC_FMC_LLD_SDRAM_Command_BurstTerminate:
607  errorCode = oC_ErrorCode_NotImplemented;
608  break;
609  case oC_FMC_LLD_SDRAM_Command_AutoRefresh:
610  if(ErrorCondition(IsRam(Data) || IsRom(Data) , oC_ErrorCode_WrongAddress))
611  {
612  command.CommandMode = CommandMode_AutoRefresh;
613  command.AutoRefreshNumber = Data->AutoRefresh.NumberOfAutoRefresh;
614  command.ModeRegisterDefinition = 0;
615  sendCommand = true;
616  errorCode = oC_ErrorCode_None;
617  }
618  break;
619  case oC_FMC_LLD_SDRAM_Command_SelfRefresh:
620  if(ErrorCondition(IsRam(Data) || IsRom(Data) , oC_ErrorCode_WrongAddress))
621  {
622  command.CommandMode = CommandMode_SelfRefresh;
623  command.AutoRefreshNumber = Data->AutoRefresh.NumberOfAutoRefresh;
624  command.ModeRegisterDefinition = 0;
625  sendCommand = true;
626  errorCode = oC_ErrorCode_None;
627  }
628  break;
629  default:
630  errorCode = oC_ErrorCode_CommandNotCorrect;
631  break;
632  }
633 
634  if(!oC_ErrorOccur(errorCode) && sendCommand == true)
635  {
636  if(ErrorCondition(SendSDRAMCommand(Timeout,&command,Result->ConfiguredBanks) , oC_ErrorCode_Timeout))
637  {
638  errorCode = oC_ErrorCode_None;
639  }
640  }
641  }
642 
643  return errorCode;
644 }
645 
646 //==========================================================================================================================================
651 //==========================================================================================================================================
652 oC_ErrorCode_t oC_FMC_LLD_FinishSDRAMInitialization( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * Result )
653 {
654  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
655 
656  if(oC_Module_TurnOnVerification(&errorCode,oC_Module_FMC_LLD))
657  {
658  if(
659  ErrorCondition( IsAddressCorrect(Config) , oC_ErrorCode_WrongConfigAddress )
660  && ErrorCondition( IsAddressCorrect(ChipInfo) , oC_ErrorCode_WrongAddress )
661  && ErrorCondition( IsRam(Result) , oC_ErrorCode_OutputAddressNotInRAM )
662  && ErrorCondition( IsExternal(Result->MemoryStart) , oC_ErrorCode_MemoryNotConfigured )
663  && ErrorCondition( Result->DataBusWidth > 0 && Result->DataBusWidth <= 4 , oC_ErrorCode_MemoryNotConfigured )
664  && ErrorCondition( Result->ConfiguredFrequency > 0 , oC_ErrorCode_MemoryNotConfigured )
665  && ErrorCondition( ChipInfo->MemoryType == oC_FMC_LLD_MemoryType_SDRAM , oC_ErrorCode_MemoryTypeNotCorrect )
666  && ErrorCondition( ChipInfo->SDRAM.NumberOfRowAddressBits >= 11 , oC_ErrorCode_RowBitsNumberNotSupported )
667  && ErrorCondition( ChipInfo->SDRAM.NumberOfRowAddressBits <= 13 , oC_ErrorCode_RowBitsNumberNotSupported )
668  && ErrorCondition( ChipInfo->SDRAM.AutoRefreshPeriod > 0 , oC_ErrorCode_AutoRefreshPeriodNotCorrect)
669  && ErrorCondition( ChipInfo->SDRAM.MaximumClockFrequency > 0 , oC_ErrorCode_WrongFrequency )
670  )
671  {
672  /* Counting maximum number of rows, that is possible for the chip */
673  uint32_t maximumNumberOfRows = oC_Bits_Mask_U32(0,ChipInfo->SDRAM.NumberOfRowAddressBits);
674 
675  /* Counting number of used rows according to the configured data bus width */
676  maximumNumberOfRows /= ChipInfo->SDRAM.DataBusWidth / Result->DataBusWidth;
677 
678  /* Counting refresh rate in number of SDCLK clock cycles between the refresh cycles */
679  uint32_t count = (uint32_t)((ChipInfo->SDRAM.AutoRefreshPeriod / ((double)maximumNumberOfRows)) * Result->ConfiguredFrequency);
680 
681  if(count <= oC_Bits_Mask_U32(0,12))
682  {
683  FMC_SDRTR->COUNT = count;
684  errorCode = oC_ErrorCode_None;
685  }
686  else
687  {
688  errorCode = oC_ErrorCode_FrequencyNotPossible;
689  }
690  }
691  }
692 
693  return errorCode;
694 }
695 
696 //==========================================================================================================================================
701 //==========================================================================================================================================
702 oC_ErrorCode_t oC_FMC_LLD_FinishNORFlashInitialization( const oC_FMC_LLD_NORFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * Result )
703 {
704  return oC_ErrorCode_NotImplemented;
705 }
706 
707 //==========================================================================================================================================
712 //==========================================================================================================================================
713 oC_ErrorCode_t oC_FMC_LLD_FinishNANDFlashInitialization( const oC_FMC_LLD_NANDFlash_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * Result )
714 {
715  return oC_ErrorCode_NotImplemented;
716 }
717 
718 //==========================================================================================================================================
723 //==========================================================================================================================================
724 oC_ErrorCode_t oC_FMC_LLD_FinishPSRAMInitialization( const oC_FMC_LLD_PSRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * Result )
725 {
726  return oC_ErrorCode_NotImplemented;
727 }
728 
729 #undef _________________________________________FUNCTIONS_SECTION__________________________________________________________________________
730 
736 #define _________________________________________LOCAL_FUNCTIONS_SECTION____________________________________________________________________
737 
738 //==========================================================================================================================================
742 //==========================================================================================================================================
743 static inline bool IsProtectionCorrect( oC_FMC_LLD_Protection_t Protection )
744 {
745  return Protection == 0 ||
746  Protection <= (oC_FMC_LLD_Protection_AllowExecute | oC_FMC_LLD_Protection_AllowRead | oC_FMC_LLD_Protection_AllowWrite);
747 }
748 
749 //==========================================================================================================================================
753 //==========================================================================================================================================
754 static inline bool IsDataBusWidthCorrect( oC_FMC_LLD_DataBusWidth_t DataBusWidth )
755 {
756  oC_STATIC_ASSERT(oC_FMC_LLD_DataBusWidth_8Bits == 1 , "data bus width must be equal to the number of used bytes!");
757  oC_STATIC_ASSERT(oC_FMC_LLD_DataBusWidth_16Bits == 2 , "data bus width must be equal to the number of used bytes!");
758  oC_STATIC_ASSERT(oC_FMC_LLD_DataBusWidth_32Bits == 4 , "data bus width must be equal to the number of used bytes!");
759  oC_STATIC_ASSERT(oC_FMC_LLD_DataBusWidth_64Bits == 8 , "data bus width must be equal to the number of used bytes!");
760 
761  return DataBusWidth == oC_FMC_LLD_DataBusWidth_8Bits
762  || DataBusWidth == oC_FMC_LLD_DataBusWidth_16Bits
763  || DataBusWidth == oC_FMC_LLD_DataBusWidth_32Bits
764  || DataBusWidth == oC_FMC_LLD_DataBusWidth_64Bits;
765 }
766 
767 //==========================================================================================================================================
771 //==========================================================================================================================================
772 static inline bool IsDataBusWidthSupported( oC_FMC_LLD_DataBusWidth_t DataBusWidth )
773 {
774  return DataBusWidth == oC_FMC_LLD_DataBusWidth_8Bits
775  || DataBusWidth == oC_FMC_LLD_DataBusWidth_16Bits
776  || DataBusWidth == oC_FMC_LLD_DataBusWidth_32Bits;
777 }
778 
779 
780 //==========================================================================================================================================
784 //==========================================================================================================================================
785 static oC_ErrorCode_t ConnectSDRAMModulePins( const oC_FMC_LLD_SDRAM_Pins_t * Pins , oC_FMC_LLD_Result_t * Result )
786 {
787  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
788 
789  oC_Procedure_Begin
790  {
791  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDCLK , oC_FMC_PinFunction_FMC_SDCLK , &Result->SDCLK ) );
792 
793  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDCKE[0] , oC_FMC_PinFunction_FMC_SDCKE0 , &Result->SDCKE[0] ) );
794  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDCKE[1] , oC_FMC_PinFunction_FMC_SDCKE1 , &Result->SDCKE[1] ) );
795 
796 
797  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDNE[0] , oC_FMC_PinFunction_FMC_SDNE0 , &Result->SDNE[0] ) );
798  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDNE[1] , oC_FMC_PinFunction_FMC_SDNE1 , &Result->SDNE[1] ) );
799 
800 
801  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 0] , oC_FMC_PinFunction_FMC_A0 , &Result->A[ 0] ) );
802  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 1] , oC_FMC_PinFunction_FMC_A1 , &Result->A[ 1] ) );
803  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 2] , oC_FMC_PinFunction_FMC_A2 , &Result->A[ 2] ) );
804  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 3] , oC_FMC_PinFunction_FMC_A3 , &Result->A[ 3] ) );
805  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 4] , oC_FMC_PinFunction_FMC_A4 , &Result->A[ 4] ) );
806  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 5] , oC_FMC_PinFunction_FMC_A5 , &Result->A[ 5] ) );
807  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 6] , oC_FMC_PinFunction_FMC_A6 , &Result->A[ 6] ) );
808  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 7] , oC_FMC_PinFunction_FMC_A7 , &Result->A[ 7] ) );
809  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 8] , oC_FMC_PinFunction_FMC_A8 , &Result->A[ 8] ) );
810  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[ 9] , oC_FMC_PinFunction_FMC_A9 , &Result->A[ 9] ) );
811  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[10] , oC_FMC_PinFunction_FMC_A10 , &Result->A[10] ) );
812  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[11] , oC_FMC_PinFunction_FMC_A11 , &Result->A[11] ) );
813  oC_Procedure_ExitIfError(ConnectModulePin( Pins->A[12] , oC_FMC_PinFunction_FMC_A12 , &Result->A[12] ) );
814 
815 
816  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 0] , oC_FMC_PinFunction_FMC_D0 , &Result->D[ 0] ) );
817  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 1] , oC_FMC_PinFunction_FMC_D1 , &Result->D[ 1] ) );
818  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 2] , oC_FMC_PinFunction_FMC_D2 , &Result->D[ 2] ) );
819  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 3] , oC_FMC_PinFunction_FMC_D3 , &Result->D[ 3] ) );
820  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 4] , oC_FMC_PinFunction_FMC_D4 , &Result->D[ 4] ) );
821  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 5] , oC_FMC_PinFunction_FMC_D5 , &Result->D[ 5] ) );
822  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 6] , oC_FMC_PinFunction_FMC_D6 , &Result->D[ 6] ) );
823  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 7] , oC_FMC_PinFunction_FMC_D7 , &Result->D[ 7] ) );
824  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 8] , oC_FMC_PinFunction_FMC_D8 , &Result->D[ 8] ) );
825  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[ 9] , oC_FMC_PinFunction_FMC_D9 , &Result->D[ 9] ) );
826  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[10] , oC_FMC_PinFunction_FMC_D10 , &Result->D[10] ) );
827  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[11] , oC_FMC_PinFunction_FMC_D11 , &Result->D[11] ) );
828  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[12] , oC_FMC_PinFunction_FMC_D12 , &Result->D[12] ) );
829  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[13] , oC_FMC_PinFunction_FMC_D13 , &Result->D[13] ) );
830  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[14] , oC_FMC_PinFunction_FMC_D14 , &Result->D[14] ) );
831  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[15] , oC_FMC_PinFunction_FMC_D15 , &Result->D[15] ) );
832  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[16] , oC_FMC_PinFunction_FMC_D16 , &Result->D[16] ) );
833  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[17] , oC_FMC_PinFunction_FMC_D17 , &Result->D[17] ) );
834  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[18] , oC_FMC_PinFunction_FMC_D18 , &Result->D[18] ) );
835  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[19] , oC_FMC_PinFunction_FMC_D19 , &Result->D[19] ) );
836  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[20] , oC_FMC_PinFunction_FMC_D20 , &Result->D[20] ) );
837  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[21] , oC_FMC_PinFunction_FMC_D21 , &Result->D[21] ) );
838  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[22] , oC_FMC_PinFunction_FMC_D22 , &Result->D[22] ) );
839  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[23] , oC_FMC_PinFunction_FMC_D23 , &Result->D[23] ) );
840  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[24] , oC_FMC_PinFunction_FMC_D24 , &Result->D[24] ) );
841  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[25] , oC_FMC_PinFunction_FMC_D25 , &Result->D[25] ) );
842  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[26] , oC_FMC_PinFunction_FMC_D26 , &Result->D[26] ) );
843  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[27] , oC_FMC_PinFunction_FMC_D27 , &Result->D[27] ) );
844  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[28] , oC_FMC_PinFunction_FMC_D28 , &Result->D[28] ) );
845  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[29] , oC_FMC_PinFunction_FMC_D29 , &Result->D[29] ) );
846  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[30] , oC_FMC_PinFunction_FMC_D30 , &Result->D[30] ) );
847  oC_Procedure_ExitIfError(ConnectModulePin( Pins->D[31] , oC_FMC_PinFunction_FMC_D31 , &Result->D[31] ) );
848 
849  oC_Procedure_ExitIfError(ConnectModulePin( Pins->BA[0] , oC_FMC_PinFunction_FMC_BA0 , &Result->BA[0] ) );
850  oC_Procedure_ExitIfError(ConnectModulePin( Pins->BA[1] , oC_FMC_PinFunction_FMC_BA1 , &Result->BA[1] ) );
851 
852  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NRAS , oC_FMC_PinFunction_FMC_SDNRAS , &Result->NRAS ) );
853  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NCAS , oC_FMC_PinFunction_FMC_SDNCAS , &Result->NCAS ) );
854  oC_Procedure_ExitIfError(ConnectModulePin( Pins->SDNWE , oC_FMC_PinFunction_FMC_SDNWE , &Result->SDNWE ) );
855 
856  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NBL[0] , oC_FMC_PinFunction_FMC_NBL0 , &Result->NBL[0] ) );
857  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NBL[1] , oC_FMC_PinFunction_FMC_NBL1 , &Result->NBL[1] ) );
858  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NBL[2] , oC_FMC_PinFunction_FMC_NBL2 , &Result->NBL[2] ) );
859  oC_Procedure_ExitIfError(ConnectModulePin( Pins->NBL[3] , oC_FMC_PinFunction_FMC_NBL3 , &Result->NBL[3] ) );
860 
861  errorCode = oC_ErrorCode_None;
862  }
863  oC_Procedure_End;
864 
865  if(oC_ErrorOccur(errorCode))
866  {
867  DisconnectModulePins(Pins->PinsArray,Result->PinsUsage,GetNumberOfPinsInStructure(oC_FMC_LLD_SDRAM_Pins_t));
868  }
869 
870  return errorCode;
871 }
872 
873 //==========================================================================================================================================
877 //==========================================================================================================================================
878 static oC_ErrorCode_t DisconnectModulePins( const oC_Pin_t * Pins , oC_FMC_LLD_PinUsage_t * PinsUsage , oC_UInt_t NumberOfPins )
879 {
880  oC_ErrorCode_t errorCode = oC_ErrorCode_None;
881 
882  for(uint32_t pinIndex = 0; pinIndex < NumberOfPins ; pinIndex++)
883  {
884  if(PinsUsage[pinIndex] == oC_FMC_LLD_PinUsage_Used)
885  {
886  oC_AssignErrorCode(&errorCode,DisconnectPin(Pins[pinIndex]));
887  }
888  }
889 
890  return errorCode;
891 }
892 
893 //==========================================================================================================================================
897 //==========================================================================================================================================
898 static bool FindFreeBanks( oC_FMC_LLD_MemoryType_t MemoryType , oC_MemorySize_t MemorySize , Bank_t * outBanks , uint8_t ** outAddress )
899 {
900  Bank_t banks = 0;
901  BankData_t foundBankData = {0};
902 
903  oC_ARRAY_FOREACH_IN_ARRAY(BankDatas,bankData)
904  {
905  if(IsBankUsed(bankData->Bank) == false)
906  {
907  if(bankData->MemoryType == MemoryType)
908  {
909  /* If this is the first bank that has been found */
910  if(foundBankData.Bank == 0)
911  {
912  foundBankData.Bank = bankData->Bank;
913  foundBankData.StartAddress = bankData->StartAddress;
914  foundBankData.EndAddress = bankData->EndAddress;
915  foundBankData.MemoryType = bankData->MemoryType;
916  foundBankData.Size = bankData->Size;
917  }
918  /* If some bank was found before */
919  else
920  {
921  if(bankData->StartAddress == foundBankData.EndAddress)
922  {
923  foundBankData.Bank |= bankData->Bank;
924  foundBankData.EndAddress = bankData->EndAddress;
925  foundBankData.Size += bankData->Size;
926  }
927  else if(bankData->EndAddress == foundBankData.StartAddress)
928  {
929  foundBankData.Bank |= bankData->Bank;
930  foundBankData.StartAddress= bankData->StartAddress;
931  foundBankData.Size += bankData->Size;
932  }
933  }
934 
935  if(foundBankData.Size >= MemorySize)
936  {
937  break;
938  }
939  }
940  }
941  }
942 
943  if(foundBankData.Size >= MemorySize)
944  {
945  banks = foundBankData.Bank;
946  *outBanks = banks;
947  *outAddress = foundBankData.StartAddress;
948  }
949 
950  return banks != 0;
951 }
952 
953 //==========================================================================================================================================
957 //==========================================================================================================================================
958 static oC_ErrorCode_t UnconfigureSDRAM( const oC_FMC_LLD_SDRAM_Config_t * Config )
959 {
960  return oC_ErrorCode_None;
961 }
962 
963 //==========================================================================================================================================
967 //==========================================================================================================================================
968 static oC_ErrorCode_t ConnectModulePin( oC_Pin_t Pin , oC_PinFunction_t PinFunction , oC_FMC_LLD_PinUsage_t * PinUsage )
969 {
970  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
971  oC_ModulePinIndex_t modulePin = 0;
972  bool pinUsed = false;
973 
974  if(Pin == oC_Pin_NotUsed && (*PinUsage) != oC_FMC_LLD_PinUsage_Required)
975  {
976  errorCode = oC_ErrorCode_None;
977  }
978  else if(ErrorCondition(oC_GPIO_LLD_IsPinDefined(Pin), oC_ErrorCode_PinNotDefined )
979  && oC_AssignErrorCode(&errorCode , oC_GPIO_LLD_CheckIsPinUsed(Pin , &pinUsed) )
980  && ErrorCondition(pinUsed == false , oC_ErrorCode_PinIsUsed )
981  && oC_AssignErrorCode(&errorCode , oC_GPIO_MSLLD_FindModulePin(Pin , oC_Channel_FMC , PinFunction , &modulePin))
982  && oC_AssignErrorCode(&errorCode , oC_GPIO_MSLLD_ConnectModulePin(modulePin) )
983  && oC_AssignErrorCode(&errorCode , oC_GPIO_LLD_SetPinsUsed(Pin) )
984  )
985  {
986  *PinUsage = oC_FMC_LLD_PinUsage_Used;
987  errorCode = oC_ErrorCode_None;
988  }
989 
990  return errorCode;
991 }
992 
993 //==========================================================================================================================================
997 //==========================================================================================================================================
998 static oC_ErrorCode_t DisconnectPin( oC_Pin_t Pin )
999 {
1000  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1001 
1002  if(
1003  oC_AssignErrorCode(&errorCode , oC_GPIO_MSLLD_SetAlternateNumber(Pin,0) )
1004  && oC_AssignErrorCode(&errorCode , oC_GPIO_LLD_SetPinsUnused(Pin) )
1005  )
1006  {
1007  errorCode = oC_ErrorCode_None;
1008  }
1009 
1010  return errorCode;
1011 }
1012 
1013 //==========================================================================================================================================
1017 //==========================================================================================================================================
1018 static uint32_t TimeToCycles( oC_Time_t Time , oC_Frequency_t Frequency )
1019 {
1020  return (uint32_t)(Time / oC_Frequency_ToTime(Frequency));
1021 }
1022 
1023 //==========================================================================================================================================
1027 //==========================================================================================================================================
1028 static bool SetTimeInCycles( uint32_t * outCycles , oC_Time_t Time , oC_Frequency_t Frequency , uint32_t Min , uint32_t Max , uint32_t Default )
1029 {
1030  bool success = false;
1031  uint32_t cycles = TimeToCycles(Time,Frequency);
1032 
1033  if(Time == 0)
1034  {
1035  *outCycles = Default;
1036  success = true;
1037  }
1038  else if(cycles >= Min && cycles <= Max)
1039  {
1040  *outCycles = cycles;
1041  success = true;
1042  }
1043 
1044  return success;
1045 }
1046 
1047 //==========================================================================================================================================
1051 //==========================================================================================================================================
1052 static bool SendSDRAMCommand( oC_Time_t * Timeout , SDRAMCommand_t * Command , Bank_t Banks )
1053 {
1054  oC_RegisterType_FMC_SDCMR_t SDCMR = { .Value = FMC_SDCMR->Value };
1055 
1056  SDCMR.MRD = Command->ModeRegisterDefinition;
1057  SDCMR.NRFS = Command->AutoRefreshNumber;
1058  SDCMR.CTB1 = (Banks & Bank_MainBank5) ? 1 : 0;
1059  SDCMR.CTB2 = (Banks & Bank_MainBank6) ? 1 : 0;
1060  SDCMR.MODE = Command->CommandMode;
1061 
1062  FMC_SDCMR->Value = SDCMR.Value;
1063 
1064  while(FMC_SDSR->BUSY && (*Timeout) > 0)
1065  {
1066  oC_CLOCK_LLD_DelayForMicroseconds(10);
1067  *Timeout = *Timeout - oC_Time_ToMicroseconds(10);
1068  }
1069 
1070  return FMC_SDSR->BUSY == 0;
1071 }
1072 
1073 //==========================================================================================================================================
1077 //==========================================================================================================================================
1078 static oC_ErrorCode_t CountSDRAMConfigVariables( const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , SDRAMConfigVariables_t * outVariables , oC_FMC_LLD_Result_t * outResult )
1079 {
1080  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1081  oC_Frequency_t currentFrequency = oC_CLOCK_LLD_GetClockFrequency();
1082 
1083  outResult->DataBusWidth = (Config->DataBusWidth == 0) ? ChipInfo->SDRAM.DataBusWidth : Config->DataBusWidth;
1084  outResult->DirectAccessProtection = Config->Protection != oC_FMC_LLD_Protection_Default ? Config->Protection :
1085  oC_FMC_LLD_Protection_AllowRead |
1086  oC_FMC_LLD_Protection_AllowWrite;
1087  outVariables->SDCR.SDCLK = ((currentFrequency/2) <= ChipInfo->SDRAM.MaximumClockFrequency) ? 2 :
1088  ((currentFrequency/3) <= ChipInfo->SDRAM.MaximumClockFrequency) ? 3 : 0;
1089 
1090  if(
1091  ErrorCondition( IsDataBusWidthCorrect ( outResult->DataBusWidth) , oC_ErrorCode_DataBusWidthNotCorrect )
1092  && ErrorCondition( IsDataBusWidthSupported( outResult->DataBusWidth) , oC_ErrorCode_DataBusWidthNotSupported )
1093  && ErrorCondition( IsDataBusWidthCorrect ( ChipInfo->SDRAM.DataBusWidth) , oC_ErrorCode_DataBusWidthNotCorrect )
1094  && ErrorCondition( ChipInfo->SDRAM.Size > 0 , oC_ErrorCode_SizeNotCorrect )
1095  && ErrorCondition( ChipInfo->SDRAM.NumberOfRowAddressBits >= 11 , oC_ErrorCode_RowBitsNumberNotSupported )
1096  && ErrorCondition( ChipInfo->SDRAM.NumberOfRowAddressBits <= 13 , oC_ErrorCode_RowBitsNumberNotSupported )
1097  && ErrorCondition( ChipInfo->SDRAM.NumberOfColumnAddressBits >= 8 , oC_ErrorCode_ColumnBitsNumberNotSupported )
1098  && ErrorCondition( ChipInfo->SDRAM.NumberOfColumnAddressBits <= 11 , oC_ErrorCode_ColumnBitsNumberNotSupported )
1099  && ErrorCondition( ChipInfo->SDRAM.NumberOfBanks == 4 || ChipInfo->SDRAM.NumberOfBanks == 2 , oC_ErrorCode_NumberOfBanksNotSupported )
1100  && ErrorCondition( IsProtectionCorrect(outResult->DirectAccessProtection) , oC_ErrorCode_ProtectionNotCorrect )
1101  && ErrorCondition( currentFrequency > 0 , oC_ErrorCode_ClockConfigurationError )
1102  && ErrorCondition( ChipInfo->SDRAM.MaximumClockFrequency > 0 , oC_ErrorCode_WrongFrequency )
1103  && ErrorCondition( ChipInfo->SDRAM.CasLatency > 0 , oC_ErrorCode_CasLatencyNotCorrect )
1104  && ErrorCondition( outVariables->SDCR.SDCLK > 0 , oC_ErrorCode_FrequencyNotPossible )
1105  )
1106  {
1107  oC_Time_t memoryClockPeriod = 0;
1108  oC_Time_t mainClockPeriod = oC_Frequency_ToTime(currentFrequency);
1109  uint32_t activeToReadWriteDelayInCycles = 0;
1110  uint32_t prechargeDelayInCycles = 0;
1111  uint32_t writeRecoveryDelayInCycles = 0;
1112  uint32_t refreshToActivateDelayInCycles = 0;
1113  uint32_t minimumSelfRefreshPeriodInCycles = 0;
1114  uint32_t exitSelfRefreshDelayInCycles = 0;
1115 
1116 
1117  /* If this assertion fails, then the function for verification data bus width does not work correctly (the 0 value is not allowed) */
1118  oC_ASSERT( outResult->DataBusWidth != 0 );
1119 
1120  outResult->ConfiguredFrequency = currentFrequency / ((oC_Frequency_t)outVariables->SDCR.SDCLK);
1121 
1122  /* Memory clock period is required for counting most of parameters */
1123  memoryClockPeriod = oC_Frequency_ToTime(outResult->ConfiguredFrequency);
1124 
1125  /* Size of the used memory can be different than chip size if we do not use all DATA pins */
1126  outResult->MemorySize = ChipInfo->SDRAM.Size;
1127  outResult->MemorySize /= ChipInfo->SDRAM.DataBusWidth / outResult->DataBusWidth;
1128 
1129 
1130  /* Prepare SDCR register value */
1131  outVariables->SDCR.NC = ChipInfo->SDRAM.NumberOfColumnAddressBits - 8;
1132  outVariables->SDCR.NR = ChipInfo->SDRAM.NumberOfRowAddressBits - 11;
1133  outVariables->SDCR.NB = ChipInfo->SDRAM.NumberOfBanks == 4 ? 1 : 0;
1134  outVariables->SDCR.MWID = outResult->DataBusWidth == oC_FMC_LLD_DataBusWidth_8Bits ? 0 :
1135  outResult->DataBusWidth == oC_FMC_LLD_DataBusWidth_16Bits ? 1 :
1136  outResult->DataBusWidth == oC_FMC_LLD_DataBusWidth_32Bits ? 2 : 3;
1137  outVariables->SDCR.CAS = ( memoryClockPeriod * 2 ) >= ChipInfo->SDRAM.CasLatency ? 1 :
1138  ( memoryClockPeriod * 3 ) >= ChipInfo->SDRAM.CasLatency ? 2 :
1139  ( memoryClockPeriod * 4 ) >= ChipInfo->SDRAM.CasLatency ? 3 : 0;
1140  outVariables->SDCR.WP = outResult->DirectAccessProtection & oC_FMC_LLD_Protection_AllowWrite ? 0 : 1;
1141  outVariables->SDCR.RBURST = ChipInfo->SDRAM.Advanced.UseBurstRead ? 1 : 0;
1142  outVariables->SDCR.RPIPE = ( mainClockPeriod * 0 ) >= ChipInfo->SDRAM.Advanced.ReadPipeDelay ? 0 :
1143  ( mainClockPeriod * 2 ) >= ChipInfo->SDRAM.Advanced.ReadPipeDelay ? 1 :
1144  ( mainClockPeriod * 3 ) >= ChipInfo->SDRAM.Advanced.ReadPipeDelay ? 2 : 3;
1145 
1146  CountSDRAMRequiredPins(ChipInfo,outResult);
1147 
1148 
1149  if(
1150  ErrorCondition( outResult->MemorySize > 0 , oC_ErrorCode_SizeNotCorrect )
1151  && ErrorCondition( outResult->MemorySize <= MAX_SDRAM_SIZE , oC_ErrorCode_SizeTooBig )
1152  && ErrorCondition( outVariables->SDCR.CAS > 0 , oC_ErrorCode_CasLatencyNotSupported )
1153  && ErrorCondition( outVariables->SDCR.RPIPE < 3 , oC_ErrorCode_ReadPipeDelayNotPossible )
1154  && ErrorCondition( outVariables->SDCR.MWID < 3 , oC_ErrorCode_DataBusWidthNotCorrect )
1155 
1156  && ErrorCondition( ChipInfo->SDRAM.CyclesToDelayAfterLoadMode >= 1 && ChipInfo->SDRAM.CyclesToDelayAfterLoadMode <= 16 , oC_ErrorCode_DelayNotPossible )
1157  && ErrorCondition( SetTimeInCycles(&activeToReadWriteDelayInCycles , ChipInfo->SDRAM.ActiveToReadWriteDelay , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1158  && ErrorCondition( SetTimeInCycles(&prechargeDelayInCycles , ChipInfo->SDRAM.PrechargeDelay , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1159  && ErrorCondition( SetTimeInCycles(&writeRecoveryDelayInCycles , ChipInfo->SDRAM.WriteRecoveryDelay , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1160  && ErrorCondition( SetTimeInCycles(&refreshToActivateDelayInCycles , ChipInfo->SDRAM.RefreshToActivateDelay , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1161  && ErrorCondition( SetTimeInCycles(&minimumSelfRefreshPeriodInCycles , ChipInfo->SDRAM.MinimumSelfRefreshPeriod , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1162  && ErrorCondition( SetTimeInCycles(&exitSelfRefreshDelayInCycles , ChipInfo->SDRAM.ExitSelfRefreshDelay , outResult->ConfiguredFrequency,1,16,1), oC_ErrorCode_DelayNotPossible )
1163 
1164  && ErrorCondition( FindFreeBanks( ChipInfo->MemoryType,
1165  outResult->MemorySize,
1166  (Bank_t*)&outResult->ConfiguredBanks,
1167  &outResult->MemoryStart) , oC_ErrorCode_NoFreeBankAvailable )
1168  )
1169  {
1170  outVariables->SDTR.TRCD = activeToReadWriteDelayInCycles - 1;
1171  outVariables->SDTR.TRP = prechargeDelayInCycles - 1;
1172  outVariables->SDTR.TWR = writeRecoveryDelayInCycles - 1;
1173  outVariables->SDTR.TRC = refreshToActivateDelayInCycles - 1;
1174  outVariables->SDTR.TRAS = minimumSelfRefreshPeriodInCycles - 1;
1175  outVariables->SDTR.TXSR = exitSelfRefreshDelayInCycles - 1;
1176  outVariables->SDTR.TMRD = ChipInfo->SDRAM.CyclesToDelayAfterLoadMode - 1;
1177 
1178  errorCode = oC_ErrorCode_None;
1179  }
1180  }
1181 
1182  return errorCode;
1183 }
1184 
1185 //==========================================================================================================================================
1189 //==========================================================================================================================================
1190 static void CountSDRAMRequiredPins( const oC_FMC_LLD_ChipParameters_t * ChipInfo , oC_FMC_LLD_Result_t * outResult )
1191 {
1192  uint32_t numberOfDataBits = outResult->DataBusWidth * 8;
1193 
1194  oC_ASSERT( IsDataBusWidthSupported(outResult->DataBusWidth) );
1195  oC_ASSERT( ChipInfo->SDRAM.NumberOfRowAddressBits >= ChipInfo->SDRAM.NumberOfColumnAddressBits );
1196 
1197  outResult->SDCLK = oC_FMC_LLD_PinUsage_Required;
1198  outResult->SDNWE = oC_FMC_LLD_PinUsage_Required;
1199  outResult->NCAS = oC_FMC_LLD_PinUsage_Required;
1200  outResult->NRAS = oC_FMC_LLD_PinUsage_Required;
1201 
1202  for(uint8_t bitIndex = 0; bitIndex < ChipInfo->SDRAM.NumberOfRowAddressBits; bitIndex++)
1203  {
1204  outResult->A[bitIndex] = oC_FMC_LLD_PinUsage_Required;
1205  }
1206 
1207  for(uint8_t bitIndex = 0; bitIndex < numberOfDataBits ; bitIndex++)
1208  {
1209  outResult->D[bitIndex] = oC_FMC_LLD_PinUsage_Required;
1210  }
1211 
1212  outResult->BA[0] = oC_FMC_LLD_PinUsage_Required;
1213  outResult->BA[1] = ChipInfo->SDRAM.NumberOfBanks == 4 ? oC_FMC_LLD_PinUsage_Required : oC_FMC_LLD_PinUsage_NotUsed;
1214 
1215  outResult->NBL[0] = oC_FMC_LLD_PinUsage_Optional;
1216  outResult->NBL[1] = oC_FMC_LLD_PinUsage_Optional;
1217  outResult->NBL[2] = oC_FMC_LLD_PinUsage_Optional;
1218  outResult->NBL[3] = oC_FMC_LLD_PinUsage_Optional;
1219 
1220  outResult->SDCKE[0] = oC_FMC_LLD_PinUsage_Optional;
1221  outResult->SDCKE[1] = oC_FMC_LLD_PinUsage_Optional;
1222 
1223  outResult->SDNE[0] = oC_FMC_LLD_PinUsage_Required;
1224  outResult->SDNE[1] = oC_FMC_LLD_PinUsage_Optional;
1225 }
1226 
1227 //==========================================================================================================================================
1231 //==========================================================================================================================================
1232 static oC_ErrorCode_t ConfigureSDRAM(const oC_FMC_LLD_SDRAM_Config_t * Config , const oC_FMC_LLD_ChipParameters_t * ChipInfo , SDRAMConfigVariables_t * outVariables , oC_FMC_LLD_Result_t * outResult )
1233 {
1234  oC_ErrorCode_t errorCode = oC_ErrorCode_ImplementError;
1235 
1236  if(
1237  ErrorCondition( outVariables->SDCR.SDCLK == 2 || outVariables->SDCR.SDCLK , oC_ErrorCode_MachineSpecificValueNotCorrect )
1238  && ErrorCondition( outResult->ConfiguredBanks & ( Bank_MainBank5 | Bank_MainBank6) , oC_ErrorCode_MachineSpecificValueNotCorrect )
1239  && ErrorCondition( oC_Machine_SetPowerStateForChannel(FMC_Channel,oC_Power_On) , oC_ErrorCode_CannotEnableChannel )
1240  )
1241  {
1242  if(outResult->ConfiguredBanks & Bank_MainBank5)
1243  {
1244  FMC_SDCR1->Value = outVariables->SDCR.Value;
1245  FMC_SDTR1->Value = outVariables->SDTR.Value;
1246 
1247  oC_ASSERT( FMC_SDCR1->Value == outVariables->SDCR.Value );
1248  oC_ASSERT( FMC_SDTR1->Value == outVariables->SDTR.Value );
1249  }
1250  if(outResult->ConfiguredBanks & Bank_MainBank6)
1251  {
1252  FMC_SDCR2->Value = outVariables->SDCR.Value;
1253  FMC_SDTR2->Value = outVariables->SDTR.Value;
1254 
1255  oC_ASSERT( FMC_SDCR2->Value == outVariables->SDCR.Value );
1256  oC_ASSERT( FMC_SDTR2->Value == outVariables->SDTR.Value );
1257  }
1258  errorCode = oC_ErrorCode_None;
1259  }
1260 
1261  return errorCode;
1262 }
1263 
1264 #undef _________________________________________LOCAL_FUNCTIONS_SECTION____________________________________________________________________
1265 
oC_Power_On
Something is powered on.
Definition: oc_stdtypes.h:252
oc_math.h
Basic math operations.
SDRAMCommand_t::CommandMode
CommandMode_t CommandMode
Command to send.
Definition: oc_fmc_lld.c:171
oC_Frequency_t
double oC_Frequency_t
type to store frequency
Definition: oc_frequency.h:76
oC_Bits_Mask_U32
#define oC_Bits_Mask_U32(FROM, TO)
Definition: oc_bits.h:73
SDRAMCommand_t
stores data for SDRAM commands
Definition: oc_fmc_lld.c:169
oc_lsf.h
The file with interface for LSF module.
oc_mem_lld.h
The file with LLD interface for the MEM driver.
oc_cfg.h
Helper macros for configurations files.
BankData_t::Bank
Bank_t Bank
Bank number mask.
Definition: oc_fmc_lld.c:144
BankData_t::MemoryType
oC_FMC_LLD_MemoryType_t MemoryType
Memory type that bank is designed for.
Definition: oc_fmc_lld.c:145
oc_fmc_lld.h
The file with LLD interface for the FMC driver.
oc_module.h
The file with interface for the module library.
oC_CLOCK_LLD_GetClockFrequency
oC_Frequency_t oC_CLOCK_LLD_GetClockFrequency(void)
returns frequency of the system clock
Definition: oc_clock_lld.c:237
BankData_t::StartAddress
void * StartAddress
Start address of the bank.
Definition: oc_fmc_lld.c:141
BankData_t::EndAddress
void * EndAddress
End address of the bank.
Definition: oc_fmc_lld.c:142
oc_clock_lld.h
The file with LLD interface for the CLOCK driver.
SDRAMConfigVariables_t
stores variables required for SDRAM configuration
Definition: oc_fmc_lld.c:181
BankData_t::Size
oC_UInt_t Size
Size of the bank.
Definition: oc_fmc_lld.c:143
oC_Module_TurnOn
static void oC_Module_TurnOn(oC_Module_t Module)
sets module as turned on
Definition: oc_module.h:170
oc_bits.h
The file with functions for the bits operation.
oC_MCS_EnterCriticalSection
static void oC_MCS_EnterCriticalSection(void)
Enters to critical section.
Definition: oc_mcs.h:755
oc_array.h
Static array definitions.
oc_string.h
The file with interface for string library.
oC_Module_TurnOffVerification
static bool oC_Module_TurnOffVerification(oC_ErrorCode_t *outErrorCode, oC_Module_t Module)
verify if module is turned off
Definition: oc_module.h:155
oC_MCS_ExitCriticalSection
static bool oC_MCS_ExitCriticalSection(void)
Exits from critical section.
Definition: oc_mcs.h:784
oC_Module_TurnOnVerification
static bool oC_Module_TurnOnVerification(oC_ErrorCode_t *outErrorCode, oC_Module_t Module)
verify if module is turned on
Definition: oc_module.h:138
SDRAMCommand_t::AutoRefreshNumber
uint32_t AutoRefreshNumber
Number of auto-refresh.
Definition: oc_fmc_lld.c:172
BankData_t
stores DATA about the bank
Definition: oc_fmc_lld.c:139
SDRAMCommand_t::ModeRegisterDefinition
uint32_t ModeRegisterDefinition
MDR data.
Definition: oc_fmc_lld.c:173
oC_CLOCK_LLD_DelayForMicroseconds
bool oC_CLOCK_LLD_DelayForMicroseconds(oC_UInt_t Microseconds)
perform a delay for us
Definition: oc_clock_lld.c:297
MB
#define MB(MBytes)
Number of MB.
Definition: oc_cfg.h:83
oC_Machine_SetPowerStateForChannel
static bool oC_Machine_SetPowerStateForChannel(oC_Channel_t Channel, oC_Power_t Power)
configures power state for machine channel
Definition: oc_machine.h:593
oc_stdtypes.h
FILE__DESCRIPTION
oC_Module_TurnOff
static void oC_Module_TurnOff(oC_Module_t Module)
sets module as turned off
Definition: oc_module.h:185